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IXDF502D1T/R 数据表(PDF) 5 Page - IXYS Corporation |
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IXDF502D1T/R 数据表(HTML) 5 Page - IXYS Corporation |
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5 / 12 page ![]() 5 IXDF502 / IXDI502 / IXDN502 PIN PACKAGE SYMBOL FUNCTION DESCRIPTION 2 1 SOIC, DIP DFN IN A A Channel Input A Channel Input signal-TTL or CMOS compatible. 3 2 SOIC, DIP DFN GND Ground The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. 4 3 SOIC, DIP DFN IN B B Channel Input B Channel Input signal-TTL or CMOS compatible. 5 4 SOIC, DIP DFN OUT B B Channel Output B Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT. 6 5 SOIC, DIP DFN VCC Supply Voltage Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from 4.5V to 30V. 7 6 SOIC, DIP DFN OUT A A Channel Output A Channel Driver output. For application purposes, this pin is connected via a resistor to a gate of a MOSFET/IGBT. Pin Description Figure 4 - Characteristics Test Diagram CAUTION: Follow proper ESD procedures when handling and assembling this component. 1 2 3 4 5 6 7 8 NC NC In A Gnd In B Out B Vcc Out A 10uF Vcc 1000 pF 1000 pF Agilent 1147A Current Probe Agilent 1147A Current Probe 0.01uF IXYS reserves the right to change limits, test conditions, and dimensions. Pin Configuration 1 2 3 4 5 6 7 8 IN A GND INB O UT A V S O UT B NC NC 8 Lead PDIP (PI) 8 Pin SOIC (SI) IXDN402 1 2 3 4 5 6 7 8 IN A GND INB O UT A V S O UT B NC NC 8 Lead PDIP (PI) 8 Pin SOIC (SI) IXDI402 1 2 3 4 5 6 7 8 IN A GND INB O UT A V S O UT B NC NC 8 Lead PDIP (PI) 8 Pin SOIC (SI) IXDF402 IXDN502 IXDI502 IXDF502 (SIA) (SIA) (SIA) 1 2 3 4 5 6 GND IN A IN B OUTA OUTB Vc c 6 Lead DFN (D1) 6 Lead DFN (D1) 6 Lead DFN (D1) (Bottom View) (Bottom View) 1 2 3 4 5 6 IN A IN B OUTA GND OUTB Vc c 1 2 3 4 5 6 OUTB Vc c IN A GND IN B OUTA NOTE: Solder tabs on bottoms of DFN packages are grounded (Bottom View) |
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