AD7652ASTZ datasheet(19/28 Pages) AD

19 / 28 page

AD7652

POWER DISSIPATION VERSUS THROUGHPUT

The CNVST trace should be shielded with ground and a low

value serial resistor (i.e., 50 Ω) termination should be added

close to the output of the component that drives this line.

Operating currents are very low during the acquisition phase,

allowing significant power savings when the conversion rate is

reduced (see

). The AD7652 automatically reduces its

power consumption at the end of each conversion phase. This

makes the part ideal for very low power battery applications.

The digital interface and the reference remain active even

during the acquisition phase. To reduce operating digital supply

currents even further, digital inputs need to be driven close to

the power supply rails (i.e., DVDD or DGND), and OVDD

should not exceed DVDD by more than 0.3 V.

Figure 25

Figure 25. Power Dissipation vs. Sampling Rate

For applications where SNR is critical, the CNVST signal should

have very low jitter. This may be achieved by using a dedicated

oscillator for CNVST generation, or to clock CNVST with a

high frequency, low jitter clock, as shown in

Figure 22

BUSY

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

02964-0-011

CNVST

SAMPLE RATE (SPS)

02965-0-037

1000000

100

10000

100000

1000

10000

100

1000

100000

PDREF = PDBUF = HIGH

CONVERSION CONTROL

Figure 26

Figure 26. Basic Conversion Timing

RESET

DATA

BUSY

02964-0-011

CNVST

shows the detailed timing diagrams of the conversion

process. The AD7652 is controlled by the CNVST signal, which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conversion

is complete. CNVST operates independently of CS and RD.

Figure 27. RESET Timing

Conversions can be automatically initiated with the AD7652. If

CNVST is held LOW when BUSY is LOW, the AD7652 controls

the acquisition phase and automatically initiates a new

conversion. By keeping CNVST LOW, the AD7652 keeps the

conversion process running by itself. It should be noted that the

analog input must be settled when BUSY goes LOW. Also, at

power-up, CNVST should be brought LOW once to initiate the

conversion process. In this mode, the AD7652 can run slightly

faster than the guaranteed 500 kSPS.

t11

BUSY

DATA

BUS

CS = RD = 0

t10

PREVIOUS CONVERSION DATA

NEW DATA

02964-0-012

CNVST

Although CNVST is a digital signal, it should be designed with

special care with fast, clean edges, and levels with minimum

overshoot and undershoot or ringing.

Figure 28. Master Parallel Data Timing for Reading (Continuous Read)

Rev. 0 | Page 19 of 28

AD7652ASTZ 数据表(PDF) 19 Page - Analog Devices

AD7652ASTZ 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

AD7652ASTZ 数据表(PDF) 19 Page - Analog Devices

AD7652ASTZ 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载