| 数据搜索系统,热门电子元器件搜索 |
|
AD7669AR 数据表(PDF) 18 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7669AR 数据表(HTML) 18 Page - Analog Devices |
|
18 / 20 page ![]() –18– REV. B AD7569/AD7669 Figure 27. Typical DAC Output Voltages for Microstepping and Direction Signals for Clockwise Rotation with the UDN-2998W ANALOG DELAY LINE—AD7569 In many applications, especially in audio systems, it is necessary to provide a delay on the input signal. The circuit of Figure 28 shows how a simple analog delay line can be implemented, based on the AD7569. The input signal is sampled using the AD7569 ADC, and converted data is loaded into the 6116 (2K 8 static ram). The inverted input clock drives a counter that selects the address for the 6116. The delay is selected by choos- ing one of the output lines of the HCT4040 counter to reset the coun-ter. This can be done using a simple switch in a manual system or by a multiplexer in a programmable delay application. Data is written to the DAC using the inverted input clock signal. Figure 28. Analog Delay Line On initial start-up, the output voltage, VO, will be invalid until the length of the delay is reached (i.e., until the counter is re- set). From this point forward, the delayed data is read from the 6116 and loaded to the DAC before the newly converted data is written into the same memory location. The input clock to the system can be a square wave of maximum input frequency 200 kHz (assuming 2 µs conversion time for the ADC). The mark/space ratio of the input clock can be varied to maximize the sampling frequency if required. The clock low time has to be equal to the conversion time and access time of the ADC plus the setup time required for the 6116. The clock high time has only to be equal to the setup time for the DAC plus the delay time through the counter and the access time of the 6116. The amount of memory used, as well as the sampling frequency, determines the maximum possible delay. Using the HCT4040, and the 6116 with an input clock frequency of 200 kHz, the maximum delay is 5 ms on a maximum input frequency of 100 kHz. Using 64K memory, with an 8 kHz input clock fre- quency, the maximum delay is 8 seconds on a maximum input frequency of 4 kHz. TRANSIENT RECORDER—AD7569 The scheme just outlined can also form the basis for a transient recorder. In this case, transients on the input signal are con- verted and stored in memory. The transient can then be recalled from memory at a later time, and the transient waveform can be recreated using the AD7569 DAC. INFINITE SAMPLE-AND-HOLD—AD7569 The AD7569 is ideal for implementing a single-chip infinite sample-and-hold function. Basically, the ADC samples and con- verts the input signal into an 8-bit digital word. The 8 bits of data are then loaded to the DAC and the sampled value is re- stored to analog form. The sampled value is held until the DAC register is updated. The full-scale matching between the ADC and the DAC on the AD7569 ensures a typical error of less than 1% between the analog input voltage and the “held” output voltage. Figure 29 shows the connections required on the AD7569 to achieve this infinite sample-and-hold function. Figure 29. Infinite Sample-and-Hold |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |