DAC8043

Rev. E | Page 14 of 16

INTERFACING TO THE MC6800

As shown in Figure 20, the DAC8043 may be interfaced to the

MC6800 by successively executing memory write instructions

while manipulating the data between writes, so that each write

presents the next bit.

In this example, the most significant bits are found in the 0000

and 0001 memory locations. The four MSBs are found in the

lower half of 0000 and the eight LSBs in 0001. The data is taken

The serial data loading is triggered by the CLK pulse, which

is asserted by a decoded memory write to the 2000 memory

location, R/W, and Φ2. A write to address location 4000

transfers data from the input register to the DAC register.

74LS138

ADDRESS

DECODER

SRI

CLK

LD

DAC8043*

16-BIT DATA BUS

R/W

Φ2

8-BIT DATA BUS

MC6800

*ANALOG CIRCUITRY OMITTED

FOR SIMPLICITY.

Figure 20. DAC8043 to MC6800 Interface

DAC8043 INTERFACE TO THE 8085

The interface of the DAC8043 to the 8085 microprocessor

is shown in Figure 21. Note that the SOD line of the micro-

processor is used to present data serially to the DAC.

Data is clocked into the DAC8043 by executing memory write

instructions. The clock input is generated by decoding Address

8000 and WR. Data is loaded into the DAC register with a

memory write instruction to Address A000.

Serial data supplied to the DAC8043 must be present in

the right-justified format in Register H and Register L of the

microprocessor.

(8)

(8)

ALE

SOD

SRI

*ANALOG CIRCUITRY OMITTED FOR

SIMPLICITY.

CLK

LD

DAC8043*

ADDRESS BUS (16)

DATA

8085

8212

WR

74LS138

ADDRESS

DECODER

5V

Figure 21. DAC8043 to 8085 Interface

DAC8043 TO THE 68000 INTERFACE

The interface of the DAC8043 to the 68000 microprocessor is

shown in Figure 22. Serial data to the DAC is taken from one

of the microprocessor’s data bus lines.

AS

VMA

VPA

UDS

SRI

CLK

LD

DAC8043*

ADDRESS BUS

DATA BUS

1/4 74HC125

68000

MICRO-

PROCESSOR

*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY.

ADDRESS

DECODE

CS

+

Figure 22. DAC8043 to 68000 Microprocessor Interface