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CDBA120SL-G 数据表(PDF) 1 Page - Comchip Technology

部件名 CDBA120SL-G
功能描述  Super Low VF SMD Schottky Barrier Rectifiers
PDF  4 Pages
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制造商  COMCHIP [Comchip Technology]
网页  http://www.comchiptech.com
标志 COMCHIP - Comchip Technology

CDBA120SL-G 数据表(HTML) 1 Page - Comchip Technology

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Super Low VF SMD Schottky Barrier Rectifiers
Reverse Voltage: 20 Volts
Forward Current: 1.0 Amp
RoHS Device
Page 1
REV: A
Features
-Ultra high-speed switching.
Mechanical data
-Case: Molded plastic, DO-214AC / SMA-F
-Terminals: Solder plated, solderable per MIL-STD-750,
method 2026.
-Polarity: Indicated by cathode band.
-Weight: 0.064 grams (Approx.)
CDBA120SL-G
QW-BL015
CDBA120SL-G
Comchip Technology CO., LTD.
Max. Repetitive peak reverse voltage
Max.
voltage
RMS
Max. Continuous
voltage
reverse
Units
Symbol
Parameter
VRRM
VRMS
VR
20
14
20
V
V
V
Max. Forward voltage @IF=1.0A
VF
0.31
V
Operating Temperature
TJ
-55 to +100
°C
-Low Profile surface mount applications
in order to optimize board space.
-Low power loss, high efficiency.
-High current capability, low forward voltage drop.
-High surge capability.
-Guardring for overvoltage protection.
Forward surge current
Reverse current
Storage temperature
A
A
mA
Parameter
Conditions
on rate load (JEDEC method)
8.3ms single half sine-wave superimposed
Forward rectified current
See Fig.1
Thermal resistance
Diode junction capacitance
VR =VRRM TA=25°C
VR =VRRM TA=100°C
f=1MHZ and applied 4V DC reverse Voltage
Junction to ambient
Symbol
IO
IFSM
IR
RθJA
CJ
TSTG
IR
MIN.
TYP.
MAX.
mA
°C/W
pF
°C
1.0
30
1.0
20
70
160
-55
+150
Units
-Epoxy: UL94-V0 rate flame retardant.
-Silicon epitaxial planar chip,metal silicon junction.
Dimensions in inches and (millimeter)
SMA-F
0.062 (1.60)
0.055 (1.40)
0.114 (2.90)
0.098 (2.50)
0.181 (4.60)
0.157 (4.00)
0.008(0.20)
0.002(0.05)
0.012 (0.30)
0.006 (0.15)
0.208 (5.28)
0.189 (4.80)
0.060 (1.52)
0.030 (0.78)
0.096 (2.44)
0.079 (2.00)
Maximum Ratings and Electrical Characteristics
Ratings at Ta=25°C unless otherwise noted.
Single phase, half wave, 60Hz, resistive or inductive loaded.
For capacitive load, derate current by 20% .
1
2
Circuit Diagram
Company reserves the right to improve product design , functions and reliability without notice.


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