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ADDI7013 数据表(PDF) 1 Page - Analog Devices |
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ADDI7013 数据表(HTML) 1 Page - Analog Devices |
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1 / 2 page ![]() Dual-Channel CCD Signal Processor with Precision Timing Core Data Sheet ADDI7013 Rev. Sp0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Differential analog inputs CDS or SHA (CDS bypass) with 7 gain settings 0 dB to 36 dB, 10-bit variable gain amplifier (VGA) 16-bit, 75 MSPS analog-to-digital converter (ADC) Precision Timing core with 210 ps resolution at 75 MHz 8 independent H-clock phases with programmable drive strength (3.6 V maximum swing) 4 general-purpose outputs (GPO) On-chip sync generator with external sync input Reduced range LVDS outputs with single clock lane 6 mm × 6 mm CSP_BGA package with 0.5 mm pitch APPLICATIONS Industrial cameras Surveillance cameras Medical imaging Professional photography GENERAL DESCRIPTION The ADDI7013 is a highly integrated, dual-channel, CCD signal processor for high speed digital imaging applications. Each channel is specified at pixel rates of up to 75 MHz and consists of a complete analog front end (AFE) with analog-to-digital conversion. The Precision Timing® core allows adjustment of the correlated double sampler (CDS) and horizontal clocks with 210 ps resolution at 75 MHz operation. There are eight independent horizontal clock outputs with programmable drive strength to support a variety of CCD timing requirements. Each analog front end includes black level clamping; a CDS; a VGA; and a 16-bit, 75 MSPS analog-to-digital converter (ADC). Operation is programmed using a 3-wire serial interface. Packaged in a space-saving, 6 mm × 6 mm, CSP_BGA, the ADDI7013 is specified over an operating temperature range of −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM Figure 1. For more information about the ADDI7013, contact Analog Devices, Inc., at afe.ccd@analog.com. H1 TO H4 HL1, HL2 RG1, RG2 GPO1 TO GPO4 INP_A INM_A CDS/ SHA VGA 0dB TO 36dB 0dB TO 18dB CLAMP VREF ADC INP_B INM_B CDS/ SHA VGA 0dB TO 36dB 0dB TO 18dB CLAMP ADC REDUCED RANGE LVDS INTERFACE VD SYNC HD SDATA SCK CLI SL Precision Timing CORE ISATG INTERNAL CLOCKS INTERNAL REGISTERS ADDI7013 DOUT0N_A DOUT0P_A DOUT0N_B DOUT0P_B DOUT1P_A DOUT1N_A DOUT1P_B DOUT1N_B TCLKP TCLKN 8 4 HORIZONTAL DRIVERS |
类似零件编号 - ADDI7013 |
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类似说明 - ADDI7013 |
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