AD538

Rev. E | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

B

3

+10V

4

A

18

D

17

16

15

+2V

5

SIGNAL GND

14

PWR GND

13

C

12

11

I

9

10

AD538

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 3.

Pin No.

Mnemonic

Description

1

I

Z

Current Input for the Z Multiplicand.

2

V

Z

Voltage Input for the Z Multiplicand.

3

B

Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X

input, or performs the equivalent logarithmic equivalent of long division.

4

+10V

+10 V Reference Voltage Output.

5

+2V

+2 V Reference Voltage Output.

6

+V

S

Positive Supply Rail.

7

–V

S

Negative Rail.

8

V

O

Output Voltage.

9

I

Current Input to the Output Amplifier.

10

V

Y

Voltage Input to the Y Multiplicand.

11

I

Y

Current Input to the Y Multiplicand.

12

C

Current Input to the Base of the Antilog Log-to-Linear Converter.

13

PWR GND

High level Power Return of the Chip.

14

SIGNAL GND

Low Level Ground Return of the Device.

15

V

X

Voltage Input of the X Multiplicand.

16

I

X

Current Input of the X Input Multiplicand.

17

D

Use for Log Ratio Function.

18

A

Use for Log Ratio Function.