ADP3605ARZ-R7 datasheet(10/12 Pages) AD

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ADP3605

Data Sheet

Rev. B | Page 10 of 12

PUMP CAPACITOR

The ADP3605 alternately charges CP to the input voltage when

CP is switched in parallel with the input supply, and then transfers

charge to CO when CP is switched in parallel with CO.

During the time CP is charging, the peak current is approximately

two times the output current. During the time CP is delivering

charge to CO, the supply current drops down to about 3 mA.

A low ESR capacitor has a much greater impact on performance

for CP than CO because current through CP is twice the CO current.

Therefore, the voltage drop due to CP is about four times the

ESR of CP times the load current. While the ESR of CO affects

the output ripple voltage, the voltage drop generated by the

ESR of CP, combined with the voltage drop due to the output

source resistance, determines the maximum available VOUT.

SHUTDOWN MODE

The output of the ADP3605 can be disabled by pulling the SD

pin (Pin 4) high to a TTL/CMOS logic compatible level that

stops the internal oscillator. In shutdown mode, the quiescent

current is reduced to 2 µA (typical). Applying a digital low level or

tying the SD pin to ground turns on the output. If the shutdown

feature is not used, Pin 4 must be tied to the ground pin.

POWER DISSIPATION

The power dissipation of the ADP3605 circuit must be limited

such that the junction temperature of the device does not exceed

the maximum junction temperature rating. Total power dissipation

is calculated as

P = (VIN − |VOUT|) IOUT + (VIN) IS

where:

IOUT and IS are output current and supply current, respectively.

VIN and VOUT are input and output voltages, respectively.

For example, assuming worst-case conditions, VIN = 6 V, VOUT =

−2.9 V, IOUT = 120 mA, and IS = 5 mA. Calculated device power

dissipation is

P ≈ (6 V − |−2.9 V|) 0.12 + (6 V) 0.005 A = 402 mW

This is far below the 660 mW power dissipation capability of

the ADP3605.

GENERAL BOARD LAYOUT GUIDELINES

Because the internal switches of the ADP3605 turn on and off

very fast, good printed circuit board (PCB) layout practices are

critical to ensure optimal operation of the device. Improper layouts

results in poor load regulation, especially under heavy loads.

Output performance can be improved by following these

simple layout guidelines:

•

Use adequate ground and power traces or planes

•

Use single point ground for device ground and input and

output capacitor grounds

•

Keep external components as close to the device as possible

•

Use short traces from the input and output capacitors to

the input and output pins, respectively

ADP3605 REGULATED ADJUSTABLE OUTPUT

VOLTAGE

The regulated output voltage is programmed by a resistor that is

inserted between the VSENSE and VOUT pins, as illustrated in

Figure 16. The inherent limit of the output voltage of a single

inverting charge pump stage is −1 times the input voltage.

The inverse (that is, negative) scaling factor of 1.00 is reduced

somewhat due to losses that increase with output current. To

increase the scaling factor to attain a more negative output voltage,

an external pump stage can be added with passive components,

as is shown in Figure 17. This single stage increases the inverse

scaling factor to a limit of two, although the diode drops limits

the ability to attain that exact 2.00 scaling factor noticeably. Even

further increases can be achieved with additional external

pump stages.

Figure 16. Adjustable Regulated Output Voltage

Figure 17. Regulated −7 V from a 5 V Input

High accuracy on the adjustable output voltage is achieved with

the use of precision trimmed internal resistors, which eliminate the

need to trim the external resistor or add a second resistor to form a

divider. The adjustable output voltage is set by

VOUT

kΩ

where VOUT is in volts and R is in kΩ.

–5

–4

–3

100

R = 24kΩ

R = 29kΩ

120

LOAD CURRENT (mA)

ADP3605

VIN = 5.0V

VOUT

VIN = 5V

CIN

4.7µF

10µF

1N5817

4.7µF

GND

ADP3605

44.2kΩ

CP+

VIN

VOUT

VSENSE

CP–

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