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THS4082CDR 数据表(PDF) 19 Page - Texas Instruments |
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THS4082CDR 数据表(HTML) 19 Page - Texas Instruments |
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19 / 32 page ![]() THS4081, THS4082 175MHz LOW POWER HIGHSPEED AMPLIFIERS SLOS274D − DECEMBER 1999 − REVISED JUNE 2001 19 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION general PowerPAD design considerations (continued) The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent power and output power. The designer should never forget about the quiescent heat generated within the device, especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 47 to Figure 50 show this effect, along with the quiescent heat, with an ambient air temperature of 50 °C. Obviously, as the ambient temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result. When using VCC = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use the heat dissipation properties of the PowerPAD . The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier package (THS4082), the sum of the RMS output currents and voltages should be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical. Figure 47 Package With θJA < = 127°C/W SO-8 Package θJA = 167°C/W Low-K Test PCB VCC = ± 5 V TJ = 150°C TA = 50°C 100 80 40 0 01 2 3 140 180 200 45 160 120 60 20 | VO | − RMS Output Voltage − V Maximum Output Current Limit Line THS4081 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS Safe Operating Area Figure 48 100 10 03 6 9 1000 12 15 Maximum Output Current Limit Line SO-8 Package θJA = 167°C/W Low-K Test PCB SO-8 Package θJA = 98°C/W High-K Test PCB TJ = 150°C TA = 50°C | VO | − RMS Output Voltage − V VCC = ± 15 V DGN Package θJA = 58.4°C/W THS4081 MAXIMUM RMS OUTPUT CURRENT vs RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS Safe Operating Area |
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