EMI2124

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8

ESD Voltage Clamping

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low

a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per

the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones

or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor

has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD

pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more

information on how ON Semiconductor creates these screenshots and how to interpret them please refer to On Semiconductor

Application Notes AND8307/D and AND8308/D.

IEC61000−4−2 Spec.

Level

Test

Voltage

(kV)

First Peak

Current

(A)

Current at

30 ns (A)

Current at

60 ns (A)

1

2

7.5

4

2

2

4

15

8

4

3

6

22.5

12

6

4

8

30

16

8

90%

10%

IEC61000−4−2 Waveform

100%

I @ 30 ns

I @ 60 ns

50 W

50 W

Cable

TVS

Oscilloscope

ESD Gun

Figure 12. Diagram of ESD Test Setup

Figure 13. 8 x 20 ms Pulse Waveform

100

90

80

70

60

50

40

30

20

10

0

020

40

60

80

t, TIME (ms)

AS THAT POINT WHERE THE

PEAK CURRENT DECAY = 8

ms