PIC12F675-IP datasheet(13/136 Pages) MICROCHIP

13 / 136 page

 2010 Microchip Technology Inc.

DS41190G-page 13

PIC12F629/675

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF

and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see the “Instruction Set Summary”.

STATUS: STATUS REGISTER (ADDRESS: 03h OR 83h)

Note 1: Bits IRP and RP1 (STATUS<7:6>) are not

used by the PIC12F629/675 and should

be maintained as clear. Use of these bits

is not recommended, since this may affect

upward compatibility with future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

Reserved

R/W-0

R-1

R/W-x

IRP

RP1

RP0

ZDC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

IRP: This bit is reserved and should be maintained as ‘0’

bit 6

RP1: This bit is reserved and should be maintained as ‘0’

bit 5

RP0: Register Bank Select bit (used for direct addressing)

0 = Bank 0 (00h - 7Fh)

1 = Bank 1 (80h - FFh)

bit 4

TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT Time-out occurred

bit 3

PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

For borrow, the polarity is reversed.

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0

C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note:

For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the

source register.

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