ADE7933 datasheet(81/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 81 of 120

ADE7978/ADE7933/ADE7932 CHIPSET

SOFTWARE RESET

Bit 7 (SWRST) in the CONFIG register (Address 0xE618)

manages the software reset functionality of the ADE7978 and

ADE7933/ADE7932 devices. The default value of this bit is 0. If

this bit is set to 1, the ADE7978 and ADE7933/ADE7932 devices

enter the software reset state. In this state, all internal registers are

reset to their default values. However, the serial port selection,

I2C or SPI, remains unchanged if the lock-in procedure was

executed before the reset (see the Serial Interface Selection

section for more information).

The ADE7978 signals the end of the reset by pulling the IRQ1

interrupt pin low and setting Bit 15 (RSTDONE) in the STATUS1

and is set to 1 when the reset ends. Write a 1 to the RSTDONE

status bit to clear the bit; the IRQ1 pin returns high.

After a software reset, all registers in the ADE7978 are reset to

their default values, the DSP is in idle mode, and Bit 7 (SWRST)

is cleared to 0. Reinitialize all ADE7978 registers, enable the

DSP RAM write protection, and start the DSP, as described in

the Initializing the Chipset section (Step 5 to Step 12). For more

information about data memory RAM protection and the run

During a software reset of the ADE7978, the ADE7978 resets

the ADE7933/ADE7932 devices while continuing to generate

the clock at the CLKOUT pin. The ADE7978 RESET_EN pin

goes low, and the VT_A, VT_B, VT_C, and VT_N pins toggle

eight times from high to low at a frequency of 4.096 MHz

(CLKIN/4). The RESET_EN, VT_A, VT_B, VT_C, and VT_N

pins are then taken high, and the reset ends.

ADE7933/ADE7932 SOFTWARE RESET

To reset only the ADE7933/ADE7932 devices without resetting

the ADE7978, use Bit 7 (ADE7933_SWRST) in the CONFIG3

ADE7932 devices by setting the RESET_EN pin low and

toggling the VT_A, VT_B, VT_C, and VT_N pins from high to

low eight times at 4.096 MHz (CLKIN/4). When the reset ends,

the ADE7933_SWRST bit is cleared to 0.

The recommended procedure to perform a software reset of the

ADE7933/ADE7932 devices only is as follows:

1. Write to the CONFIG3 register with Bit 7 (ADE7933_

SWRST) set to 1.

2. Read back the CONFIG3 register until Bit 7 reads as 0,

indicating that the reset has ended.

LOW POWER MODE

Under certain conditions, it may be desirable to lower the

current consumption of the chipset; in this case, the ADE7978

and ADE7933/ADE7932 can be set to a low power mode.

To enter low power mode, set Bit 6 (CLKOUT_DIS) and Bit 7

(ADE7933_SWRST) in the CONFIG3 register (Address 0xE708)

to 1. The ADE7978 stops generating the clock to the ADE7933/

ADE7932 devices and places them in the reset state.

To exit the low power mode, clear Bit 6 (CLKOUT_DIS) and

Bit 7 (ADE7933_SWRST) in the CONFIG3 register to 0. During

low power mode, the ADE7978 registers maintain their config-

urations, so they do not need to be reinitialized.

ADE7933 数据表(PDF) 81 Page - Analog Devices

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