PIC12F635ESS datasheet(94/234 Pages) MICROCHIP

94 / 234 page

PIC12F635/PIC16F636/639

DS41232D-page 92

9.1

EECON1 AND EECON2 Registers

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are

non-implemented and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal

operation. In these situations, following Reset, the user

can check the WRERR bit, clear it and rewrite the

location. The data and address will be cleared.

Therefore, the EEDAT and EEADR registers will need

to be re-initialized.

Interrupt flag, EEIF bit of the PIR1 register, is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

Note:

The

EECON1,

EEDAT

and

EEADR

registers should not be modified during a

data EEPROM write (WR bit = 1).

EECON1: EEPROM CONTROL REGISTER

U-0

R/W-x

R/W-0

R/S-0

—

WRERR

WREN

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

Unimplemented: Read as ‘0’

bit 3

WRERR: EEPROM Error Flag bit

= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

= The write operation completed

bit 2

WREN: EEPROM Write Enable bit

= Allows write cycles

= Inhibits write to the data EEPROM

bit 1

WR: Write Control bit

= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only

be set, not cleared, in software.)

= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set, not cleared, in software.)

= Does not initiate an EEPROM read

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