5895

8-BIT SERIAL-INPUT,

LATCHED DRIVERS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

TIMING CONDITIONS

A.

Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) ................................................................. 75 ns

B.

Minimum Data Active Time After Clock Pulse

(Data Hold Time) ..................................................................... 75 ns

C.

Minimum Data Pulse Width ........................................................ 150 ns

D.

Minimum Clock Pulse Width ...................................................... 150 ns

E.

Minimum Time Between Clock Activation and Strobe ............... 300 ns

F.

Minimum Strobe Pulse Width ..................................................... 100 ns

G.

Typical Time Between Strobe Activation and

Output Transition .................................................................... 1.0

Serial Data present at the input is transferred to the shift register

on the logic “0” to logic “1” transition of the CLOCK input pulse. On

succeeding CLOCK pulses, the registers shift data information towards

the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the

input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective

latch when the STROBE is high (serial-to-parallel conversion). The

latches will continue to accept new data as long as the STROBE is

held high. Applications where the latches are bypassed (STROBE tied

high) will require that the OUTPUT ENABLE input be high during serial

data entry.

When the OUTPUT ENABLE input is high, all of the output buffers

are disabled (OFF) without affecting the information stored in the

latches or shift register. With the OUTPUT ENABLE input low, the

outputs are controlled by the state of their respective latches.

Dwg. No. A-12,649A

E

F

CLOCK

DATA IN

STROBE

BLANKING

A

D

B

C

G