LPV321 datasheet(12/28 Pages) TI1

12 / 28 page

LPV321, LPV324-N, LPV358-N

SNOS413D – AUGUST 2000 – REVISED MARCH 2013

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In Figure 40, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more

phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO

resistor value, the more stable VOUT will be. Figure 41 is an output waveform of Figure 40 using 100 kΩ for RISO

and 1000 pF for CL.

Figure 41. Pulse Response of the LPV324 Circuit in Figure 40

The circuit in Figure 42 is an improvement to the one in Figure 40 because it provides DC accuracy as well as

AC stability. If there were a load resistor in Figure 40, the output would be voltage divided by RISO and the load

resistor. Instead, in Figure 42, RF provides the DC accuracy by using feed-forward techniques to connect VIN to

RL. Caution is needed in choosing the value of RF due to the input bias current of the LPV321-N/358/324. CF and

RISO serve to counteract the loss of phase margin by feeding the high frequency component of the output signal

back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Increased

capacitive drive is possible by increasing the value of CF. This in turn will slow down the pulse response.

Figure 42. Indirectly Driving A Capacitive Load with DC Accuracy

Input Bias Current Cancellation

The LPV321-N/358/324 family has a bipolar input stage. The typical input bias current of LPV321-N/358/324 is

1.5 nA with 5V supply. Thus a 100 k

Ω input resistor will cause 0.15 mV of error voltage. By balancing the resistor

values at both inverting and non-inverting inputs, the error caused by the amplifier's input bias current will be

reduced. The circuit in Figure 43 shows how to cancel the error caused by input bias current.

Figure 43. Cancelling the Error Caused by Input Bias Current

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LPV321 数据表(PDF) 12 Page - Texas Instruments