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Specifications subject to change

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Copyright © 2012, Triune Systems, LLC

TS33001/2

Version 1.3

Power Good Output, PG

This is an open drain, active high output. The switched mode output voltage is monitored and the PG line will remain low

comparator detects the output voltage is above the desired threshold, an internal 10mSec delay timer is activated and the

again. If EN is pulled low, the VCC input undervoltage trips, or Thermal Shutdown is reached, the PG pin will immediately

be pulled low.

nLow Power Mode Output, nLP

This is an input to force the PWM mode when light load is on the output. The PFM low power mode has higher output

voltage ripple, which is some applications may be unacceptable. If low ripple is needed on the output this pin can be tied to

VCC input, or switched above 2.2V during operation to force the device into normal PWM mode.

INTERNAL PROTECTION DETAILS

Internal Current Limit

Current limit is always active when the regulator is enabled. High side current limit will shorten the high side on time and

tri-state the high side. Additionally, low side current limit will protect the low side FET and turn off the switch if current

limit is sensed on the low side switch. Since the output is fully synchronous, the current limit is protected on the low side in

both the positive and negative direction.

Soft Start

Soft start ensures current limit does not prevent regulator startup and minimize overshoot at startup. The typical startup

time is 925us. These values do not change with output voltage, current limit settings, or adjustable/fixed mode. The soft

start is re-triggered with the any rising edge that enables the regulator, including the EN input pins, thermal shutdown, VCC

Undervoltage, or a VCC Power cycle.

Thermal Shutdown

If the temperature of the die exceeds 170C, the VSW outputs will tri-state to protect the device from damage. The PG and all

other protection circuitry will stay active to inform the system of the failure mode. Once the device cools to 160C, the

device will attempt to start up again, following the normal soft start sequence with 10ms delay on PG. If the device reaches

170C, the shutdown/restart sequence will repeat.

Output Overvoltage

If the output of the regulator exceeds 106% of the regulation voltage, the VSW outputs will tri-state to protect the device

from damage. This check occurs at the start of each switching cycle. If it occurs during the middle of a cycle, the switching

for that cycle will complete, and the VSW outputs will tri-state at the beginning of the next cycle.

VCC Under-Voltage Lockout

The device is held in the off state until VCC reaches 2.2V. There is a 200mV hysteresis on this input, which requires the

input to fall below 2V before the device will disable.

PERFORMANCE RESULTS

Startup Plots - TBD

Switching Plots -TBD

Load Transient Plots - TBD

Line Transient Plots - TBD

Efficiency Plots - TBD

OSC frequency across temp -TBD

Output voltage across temp –TBD

Line Regulation – TBD

Load Regulation – TBD