AD8557

Rev. C | Page 16 of 24

OPEN WIRE FAULT DETECTION

The inputs to A1 and A2, VNEG and VPOS, each have a com-

parator to detect whether VNEG or VPOS exceeds a threshold

voltage, nominally VDD − 1.1 V. If VNEG > (VDD − 1.1 V) or

VPOS > (VDD − 1.1 V), VOUT is clamped to VSS. The output

current limit circuit is disabled in this mode, but the maximum

sink current is approximately 10 mA when VDD = 5 V. The

inputs to A1 and A2, VNEG and VPOS, are also pulled up to

VDD by currents IP1 and IP2. These are both nominally 16 nA

and matched to within 3 nA. If the inputs to A1 or A2 are

accidentally left floating, as with an open wire fault, IP1 and IP2

pull them to VDD, which would cause VOUT to swing to VSS,

allowing this fault to be detected. It is not possible to disable IP1

and IP2, nor the clamping of VOUT to VSS, when VNEG or

VPOS approaches VDD.

SHORTED WIRE FAULT DETECTION

The AD8557 provides fault detection in the case where VPOS,

VNEG, or VCLAMP shorts to VDD and VSS. Figure 46 shows

the voltage regions at VPOS, VNEG, and VCLAMP that trigger

an error condition. When an error condition occurs, the VOUT

pin is shorted to VSS. Table 8 lists the voltage levels shown in

Figure 46.

VPOS

VNEG

VSS

VINL

VINH

VDD

VSS

VCLL

VDD

VCLAMP

VSS

VINL

VINH

VDD

ERROR

ERROR

NORMAL

ERROR

NORMAL

ERROR

ERROR

NORMAL

Figure 46. Voltage Regions at VPOS, VNEG, and VCLAMP

that Trigger a Fault Condition

Table 8. Typical VINL, VINH, and VCLL Values

(VDD = 5 V)

Voltage

Min (V)

Max (V)

VOUT Condition

VINH

3.9

4.2

Short to VDD fault detection

VINL

0.195

0.55

Short to VSS fault detection

VCLL

1.0

1.2

Short to VSS fault detection

FLOATING VPOS, VNEG, OR VCLAMP FAULT

DETECTION

A floating fault condition at the VPOS, VNEG, or VCLAMP

pins is detected by using a low current to pull a floating input

into an error voltage range, defined in the previous section. In

this way, the VOUT pin is shorted to VSS when a floating input

is detected. Table 9 lists the currents used.

Table 9. Floating Fault Detection at VPOS, VNEG,

and VCLAMP

Pin

Typical Current

Goal of Current

VPOS

16 nA pull-up

Pull VPOS above VINH

VNEG

16 nA pull-up

Pull VNEG above VINH

VCLAMP

0.2 µA pull-down

Pull VCLAMP below VCLL

DEVICE PROGRAMMING

Digital Interface

The digital interface allows the first stage gain, second stage

gain, and output offset to be adjusted and allows desired values

for these parameters to be permanently stored by selectively

blowing polysilicon fuses. To minimize pin count and board

space, a single-wire digital interface is used. The digital input

pin, DIGIN, has hysteresis to minimize the possibility of

inadvertent triggering with slow signals. It also has a pull-down

current sink to allow it to be left floating when programming is

not being performed. The pull-down ensures inactive status of

the digital input by forcing a dc low voltage on DIGIN.

A short pulse at DIGIN from low to high and back to low again,

such as between 50 ns and 10 µs long, loads a 0 into a shift

register. A long pulse at DIGIN, such as 50 µs or longer, loads a

1 into the shift register. The time between pulses should be at

least 10 µs. Assuming VSS = 0 V, voltages at DIGIN between

VSS and 0.2 × VDD are recognized as a low, and voltages at

DIGIN between 0.8 × VDD and VDD are recognized as a high.

A timing diagram example, Figure 47, shows the waveform for

entering Code 010011 into the shift register.

CODE

0

1

0

0

1

1

WAVEFORM

Figure 47. Timing Diagram for Code 010011