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MP3397 数据表(PDF) 13 Page - Monolithic Power Systems |
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MP3397 数据表(HTML) 13 Page - Monolithic Power Systems |
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13 / 16 page ![]() MP3397—4-STRING, MAX 350mA/STRING WHITE LED DRIVER MP3397 Rev. 1.01 www.MonolithicPower.com 13 9/4/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. Figure 4—Direct PWM Dimming Table 1 shows the PWM dimming duty Range with different PWM dimming frequency. Tab 1 The Range of PWM Dimming Duty fPWM(Hz) Dmin Dmax 100<f 200 0.30% 100% 200<f 500 0.75% 100% 500<f 1k 1.50% 100% 1k<f 2k 3.00% 100% 2k<f 5k 7.50% 100% 5k<f 10k 15.00% 100% 10k<f 20k 30.00% 100% 2. DC Input PWM Dimming For DC input PWM dimming, apply an analog signal (ranging from 0.2 V to 1.2V) to the DBRT pin to modulate the LED current directly. If the DBRT voltage falls below 0.2V, the PWM duty cycle will be 0%. If the DBRT voltage goes above 1.2V, the output will be 100% (See Figure 5). The capacitor on BOSC pin sets the frequency of the internal triangle waveform according to the equation. fBOSC (kHz)= 3.5 / CBOSC(nF) Chose a dimming frequency in the range of 100Hz to 20kHz. Figure 5—DC input PWM Dimming Expanding LED Channels The MP3397 can expand the number of LED channels by using two or three MP3397s in parallel. To connect two MP3397s for a total of 8 LED strings, tie the VCC pins of the master IC and the slave IC together to power the slave IC internal logic circuitry. Tie the COMP pins of the slave IC and the master IC together to regulate the voltage of all 8 strings LEDs. The slave IC MOSFET driving signals are not used; the boost converter can be only driven by the master IC. Do not leave the ISENSE pin of the slave IC floating; tie it to ground. Apply the EN and DIM signals to both ICs. For best results, use external PWM dimming mode for synchronized and accurate dimming. Layout Considerations The circuit layout for the MP3397 requires special attention to reduce EMI noise. The loop from the external MOSFET (M1), through the output diode (D1) and the output capacitor (C2, C3) carry a high-frequency pulse current and must be as small and short as possible (See Figure 6). Figure 6—Layout Consideration All logic signals return to the signal ground. In order to reduce the effects of noise, separate power ground (PGND) and signal ground (GND), and connect PGND and GND together through single point. |
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