MP4652—HIGH PERFORMANCE OFF-LINE TV LED DRIVER

MP4652 Rev.1.01

www.MonolithicPower.com

13

9/23/2011

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© 2011 MPS. All Rights Reserved.

Figure 5 shows synchronized PWM dimming with

DC input. The synchronizing signal is filtered by a

high pass filter. Its rising edge is caught and used

to synchronize the triangle waveform on the BFS

pin. The synchronizing frequency should be

higher than that set by BFS pin and the

amplitude of the synchronizing signal should be

higher than 1.4V.

Table 1—Function Mode

Pin Connection

Function

PWMIN

BFS

SYNC

PWM dimming with

DC Input Voltage

*0V to

1.2V

GND

PWM dimming with

DC Input Voltage

and Synchronizing

frequency

*0V to

1.2V

R,C,D

network

PWM dimming with

direct PWM input

PWM

To VCC

through

20kΩ

resistor

GND

Note:

Pin 11 (EN):

Pull this pin high to enable the chip, and pull it

low to disable the chip.

Pin 12 (VIN):

Supply voltage input. Bypass the supply voltage

with a 0.1μF or larger ceramic capacitor

Pin 13 (VCC):

This pin provides the gate driver supply voltage.

Its typical value is 9.7V. Connect a 1μF or greater

ceramic capacitor to this pin to bypass the supply

voltage. This voltage is also used to supply the

external control circuit.

Pin 14(GL), Pin 16 (GR):

Gate driver signals output. GL and GR are 180-

degree phase-shifted driver signals. GL and GR

can directly drive the external MOSFETs in the

off-line system through a gate driver transformer

with enhanced driver capability. Connect two

5.1Ω resistors in series with GL and GR to

reduce the EMI noise.

Place a 2.2nF Y capacitor between the primary

reference ground and the secondary reference

ground.