IXDN514PI datasheet(5/12 Pages) IXYS

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IXDI514 / IXDN514

Pin Description

CAUTION: Follow proper ESD procedures when handling and assembling this component.

* The following notes are meant to define the conditions for the θ

J-A, θJ-C and θJ-S values:

1) The

J-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the

resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards

and the values would be lower with natural convection. For the 6-Lead DFN package, the

J-A value supposes the DFN package is soldered

on a PCB. The

J-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance

to the die, it is easy to reduce the

J-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W

easily, and potentially even lower. The

J-A for DFN on PCB without heatsink or thermal management will vary significantly with size,

construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.

J-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not

published for the PDIP and SOIC packages. The

J-C for the DFN packages are important to show the low thermal resistance from junction to

the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.

3) The

J-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.

The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the

U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was

given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the

DFNpackage.

SYMBOL

FUNCTION

DESCRIPTION

VCC

Supply Voltage

Positive power-supply voltage input. This pin provides power to the

entire chip. The range for this voltage is from 4.5V to 30V.

Input

Input signal-TTL or CMOS compatible.

OUT

Output

Driver Output. For application purposes, this pin is connected,

through a resistor, to Gate of a MOSFET/IGBT.

GND

Ground

The system ground pin. Internally connected to all circuitry, this pin

provides ground reference for the entire chip. This pin should be

connected to a low noise analog ground plane for optimum

performance.

Figure 3 - Characteristics Test Diagram

5.0V

Vcc

IXDI414

IXDN414

Vcc

Agilent 1147A

Current Probe

15nF

10uF

25V

IXDI514

IXDN514

2500 pf

IXDN514PI 数据表(PDF) 5 Page - IXYS Corporation

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