ADP1607

Data Sheet

Rev. C | Page 14 of 16

LAYOUT GUIDELINES

1

2

3

4

5

6

EN

GND

SW

VOUT

FB

VIN

R1

0402

R2

0402

0402

0402

3.0mm

ADP1607

TOP VIEW

7

EPAD

L

2.2µH

0805

Figure 26. ADP1607 Recommended Layout Showing the Smallest Footprint

For high efficiency, good regulation, and stability, a well-

designed printed circuit board layout is required.

Use the following guidelines when designing printed circuit

boards (also see Figure 24 for a block diagram and Figure 2 for

a pin configuration).

•

GND. This minimizes noise injected into the part from

board parasitic inductance.

•

inductor to SW as short as possible.

•

Place the feedback resistors, R1 and R2, as close to FB as

possible to prevent noise pickup. Connect the ground of

the feedback network directly to an AGND plane that

makes a Kelvin connection to the GND pin.

•

Avoid routing high impedance traces from feedback

resistors near any node connected to SW or near the

inductor to prevent radiated noise injection.

•

and GND. This minimizes noise injected into the part from

board parasitic inductance.

•

Connect Pin 7 (EPAD) and GND to a large copper plane

for proper heat dissipation.