MP8044 - 22V, 4A DUAL CHANNEL POWER HALF-BRIDGE

M8044 Rev. 1.0

www.MonolithicPower.com

4

5/5/2010

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© 2010 MPS. All Rights Reserved.

PIN FUNCTIONS

Pin #

Name

Description

1

POR-VFB

Feedback Point for Power-On-Reset Comparator. An external resistor is connected

between the supply to be monitored and this pin.

2

AGND1

Analog Ground 1.

3

PWM1

Driver Logic Input 1. Drive PWM1 with the signal that controls the MP8044 SW1.

Drive PWM high to turn on the high side switch; drive PWM low to turn on the

low-side switch.

4

STBYB

Standby Input. Default low (internal pull-down). If driven high, the output of the drivers

is determined by the PWM1/2. If driven low, the output of both drivers is high

impedance.

5

PWM2

Driver Logic Input 2. Drive PWM2 with the signal that controls the MP8044 SW2.

Drive PWM high to turn on the high side switch; drive PWM low to turn on the

low-side switch

6

FAULTB

Fault Output. A low output at FAULTB indicates that the MP8044 has detected an

over temperature or over current condition. This output is open drain.

7

SHDNB

Shutdown Input. When low, the IC will be shut off.

8

AGND2

Analog Ground 2.

9

POR-OUT

Output of the Power-On-Reset. A high indicates the voltage at POR_VFB is lower

than 1.25V.

10

VDR2

Gate Drive Supply Bypass. The voltage at VDR2 is supplied from an internal

regulator from its respective VSP. VDR2 powers the internal circuitry and internal

MOSFET gate drive for its respective SW2 stage. Bypass VDR2 to PGND with a

0.1μF to 10μF capacitor.

11

BST2

Bootstrap Supply. BST2 powers the high-side gate of the SW2 stage. Connect a

0.1μF or greater capacitor between BST2 and SW2.

12

PGND2

Power Ground of channel 2. Connect the exposed pad on bottom side to the ground

plane.

13

SW2

Switched Output 2. Connect the output LC filter to SW2. SW2 is valid approximately

100µs after VSP goes high.

14,15, 16

VSP

Power Supply Input. Connect VSP to the positive side of the input power supply.

Bypass VSP to PGND as close to the IC as possible.

17

SW1

Switched Output 1. Connect the output LC filter to SW1. SW1 is valid approximately

100µs after VSP goes high.

18

PGND1

Power Ground of Channel 1. Connect the exposed pad on bottom side to the ground

plane.

19

BST1

Bootstrap Supply. BST1 powers the high-side gate of the SW1 stage. Connect a

0.1μF or greater capacitor between BST1 and SW1.

20

VDR1

Gate Drive Supply Bypass. The voltage at VDR1 is supplied from an internal

regulator from its respective VSP. VDR1 powers the internal circuitry and internal

MOSFET gate drive for its respective SW1 stage. Bypass VDR1 to PGND with a

0.1μF to 10μF capacitor.