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MP9151GD 数据表(PDF) 10 Page - Monolithic Power Systems |
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MP9151GD 数据表(HTML) 10 Page - Monolithic Power Systems |
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10 / 19 page ![]() MP9151 – 20V, 4A SYNCHRONOUS STEP-DOWN CONVERTER MP9151 Rev. 1.0 www.MonolithicPower.com 10 3/20/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. OPERATION The MP9151 is a high frequency synchronous rectified step-down switch mode converter with built in internal power MOSFETs. It offers a very compact solution to achieve more than 4A continuous output current over a wide input supply range with excellent load and line regulation. The MP9151 operates in a fixed frequency, peak current control mode to regulate the output voltage. A PWM cycle is initiated by the internal clock. The integrated high-side power MOSFET is turned on and remains on until its current reaches the value set by the COMP voltage. When the power switch is off, it remains off until the next clock cycle starts. If, in 95% of one PWM period, the current in the power MOSFET does not reach the COMP set current value, the power MOSFET will be forced to turn off. Error Amplifier The error amplifier compares the FB pin voltage with the internal 0.795V reference (REF) and outputs a current proportional to the difference between the two. This output current is then used to charge or discharge the internal compensation network to form the COMP voltage, which is used to control the power MOSFET current. The optimized internal compensation network minimizes the external component counts and simplifies the control loop design. Internal Regulator Most of the internal circuitries are powered from the 5V internal regulator. This regulator takes the VIN input and operates in the full VIN range. When VIN is greater than 5.0V, the output of the regulator is in full regulation. When VIN is lower than 5.0V, the output decreases, a 1uF ceramic capacitor for decoupling purpose is required. Enable Control The MP9151 has a dedicated enable control pin (EN): pulling it high enables the IC, pulling it low disables it. Float EN for automatic start up. EN must be pulled low to disable the part. The EN pin is clamped internally using a 6.7V series-Zener-diode as shown in Figure 2 Connect the EN input pin through a pullup resistor to any voltage connected to the VIN pin such that the pullup resistor limits the EN input current to less than 100µA. For example, connecting 12V to VIN, RPULLUP ≥ (12V – 6.7V)/100µA = 53kΩ. Connecting the EN pin is directly to a voltage source without any pullup resistor requires limiting the amplitude of the voltage source to below 6V to prevent damage to the Zener diode. Figure 2: Zener Diode between EN and GND The EN pin also features an internal 2.3 μA current source. Connect a capacitor to the EN pin for delayed startup. When VIN exceeds the input UVLO, an internal 2.3 μA current source charges the external capacitor. The external capacitor connects to the non-inverting input of a comparator. The part is enabled once the capacitor voltage exceeds the 1.5V internal reference voltage. Power Good Indicator The MP9151 has an open drain pin for power good indicator. When FB pin is higher than 90% of regulation voltage, 0.795V, PG pin is pulled up to VCC by the external resistor. If FB pin voltage drop down to 80% of the regulation voltage, PG pin is pulled down to ground by an internal MOS FET. Under-Voltage Lockout (UVLO) Under-voltage lockout (UVLO) is implemented to protect the chip from operating at insufficient supply voltage. The MP9151 UVLO comparator monitors the output voltage of the internal regulator, VCC. The UVLO rising threshold is about 4.1V while its falling threshold is a consistent 3.25V. |
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