MP28313 – 2A, 16V, 340KHz SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

MP28313 Rev. 1.5

www.MonolithicPower.com

9

9/27/2010

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2010 MPS. All Rights Reserved.

The DC gain of the voltage feedback loop is

given by:

OUT

FB

EA

CS

LOAD

VDC

V

V

A

G

R

A

×

×

×

=

The system has two poles of importance. One

is due to the compensation capacitor (C3,

Figure2) and the output resistor of the error

amplifier, and the other is due to the output

capacitor and the load resistor. These poles are

located at:

VEA

EA

1

P

A

3

C

2

G

f

×

×

π

=

LOAD

2

P

R

2

C

2

1

f

×

×

π

=

Where

is

the

error

amplifier

transconductance.

The system has one zero of importance, due to the

compensation capacitor (C3) and the compensation

resistor (R3). This zero is located at:

3

R

3

C

2

1

Z

×

×

π

=

The system may have another zero of

importance, if the output capacitor has a large

capacitance and/or a high ESR value. The zero,

due to the ESR and capacitance of the output

capacitor, is located at:

ESR

ESR

R

2

C

2

1

f

×

×

π

=

In this case, a third pole set by the

compensation capacitor (C6, Figure2) and the

compensation

resistor

(R3)

is

used

to

compensate the effect of the ESR zero on the

loop gain. This pole is located at:

3

R

6

C

2

1

P

×

×

π

=

The goal of compensation design is to shape

the converter transfer function to get a desired

loop gain. The system crossover frequency

where the feedback loop has the unity gain is

important. Lower crossover frequencies result

in slower line and load transient responses,

while higher crossover frequencies could cause

system instability. A good rule of thumb is to set

the crossover frequency below one-tenth of the

switching frequency.

To optimize the compensation components, the

following procedure can be used.

1. Choose the compensation resistor (R3,

Figure2) to set the desired crossover frequency.

Determine the R3 value by the following

equation:

FB

OUT

CS

EA

S

FB

OUT

CS

EA

C

V

V

G

G

f

1

.

0

2

C

2

V

V

G

G

f

2

C

2

3

R

×

×

×

×

×

π

<

×

×

×

×

π

=

which is typically below one tenth of the

switching frequency.

2. Choose the compensation capacitor (C3,

Figure2) to achieve the desired phase margin.

For applications with typical inductor values,

forth of the crossover frequency provides

sufficient phase margin.

Determine the C3 value by the following equation:

C

f

3

R

2

4

3

C

×

×

π

>

Where R3 is the compensation resistor.

3. Determine if the second compensation

capacitor (C6, Figure2) is required. It is required

if the ESR zero of the output capacitor is

located at less than half of the switching

frequency, or the following relationship is valid:

2

f

R

2

C

2

1

S

ESR

<

×

×

π

If this is the case, then add the second

compensation capacitor (C6, Figure2) to set the

Determine the C6 value by the equation:

3

R

R

2

C

6

C

ESR

×

=