24LC21 datasheet(7/24 Pages) MICROCHIP

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 2004 Microchip Technology Inc.

DS21095J-page 7

24LC21

3.1.6

SLAVE ADDRESS

After generating a Start condition, the bus master trans-

mits the slave address consisting of a 7-bit device code

‘1010’ for the 24LC21, followed by three “don’t care”

bits.

The eighth bit of slave address determines if the master

device wants to read or write to the 24LC21 (Figure 3-5).

The 24LC21 monitors the bus for its corresponding

slave

address

all

the

time.

generates

Acknowledge bit if the slave address was true and it is

not in a programming mode.

FIGURE 3-5:

CONTROL BYTE

ALLOCATION

4.0

WRITE OPERATION

4.1

Byte Write

Following the Start signal from the master, the slave

address (4 bits), the “don’t care” bits (3 bits) and the

R/W bit which is a logic low, is placed onto the bus by

the

master

transmitter.

This

indicates

the

addressed slave receiver that a byte with a word

address will follow after it has generated an Acknowl-

edge bit during the ninth clock cycle. Therefore, the

next byte transmitted by the master is the word

address and will be written into the address pointer of

the 24LC21. After receiving another Acknowledge

signal from the 24LC21 the master device will transmit

the data word to be written into the addressed mem-

ory location. The 24LC21 acknowledges again and

the master generates a Stop condition. This initiates

the internal write cycle, and during this time the

24LC21 will not generate Acknowledge signals

(Figure 4-1).

It is required that VCLK be held at a logic high level in

order to program the device. This applies to byte write

and page write operation. Note that VCLK can go low

while the device is in its self-timed program operation

and not affect programming.

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24LC21 in the same way as

in a byte write. But instead of generating a Stop condi-

tion the master transmits up to eight data bytes to the

24LC21, which are temporarily stored in the on-chip

page buffer and will be written into the memory after the

master has transmitted a Stop condition. After the

receipt of each word, the three lower order address

pointer bits are internally incremented by one. The

higher order five bits of the word address remains

constant. If the master should transmit more than eight

words prior to generating the Stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the Stop condition is received an

internal write cycle will begin (Figure 4-3).

Operation

Control Code

Chip Select

R/W

Read

1010

xxx

Write

1010

xxx

SLAVE ADDRESS

101

R/W

Start

Read/Write

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