AM28F010 datasheet(2/35 Pages) AMD

2 / 35 page

Am28F010

minutes required for EPROM erasure using ultra-violet

light are eliminated.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine

which controls the erase and programming circuitry.

During write cycles, the command register internally

latches address and data needed for the programming

and erase operations. For system design simplifica-

tion, the Am28F010 is designed to support either WE#

or CE# controlled writes. During a system write cycle,

addresses are latched on the falling edge of WE# or

CE# whichever occurs last. Data is latched on the ris-

ing edge of WE# or CE# whichever occurs first. To

simplify the following discussion, the WE# pin is used

as the write cycle control pin throughout the rest of

this text. All setup and hold times are with respect to

the WE# signal.

AMD’s Flash technology combines years of EPROM

and EEPROM experience to produce the highest levels

of quality, reliability, and cost effectiveness. The

Am28F010 electrically erases all bits simultaneously

using Fowler-Nordheim tunneling. The bytes are pro-

grammed one byte at a time using the EPROM pro-

gramming mechanism of hot electron injection.

BLOCK DIAGRAM

PRODUCT SELECTOR GUIDE

Family Part Number

Am28F010

Speed Options (VCC = 5.0 V ± 10%)

-70

-90

-120

-150

-200

Max Access Time (ns)

120

150

200

# (E#) Access (ns)

120

150

200

# (G#) Access (ns)

Erase Voltage

Switch

Input/Output

Buffers

Data

Latch

Y-Gating

1,048,576 Bit

Cell Matrix

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Program

Voltage Switch

State

Control

Command

A0–A16

DQ0–DQ7

VCC

VSS

11559H-1

Low VCC

Detector

Program/Erase

Pulse Timer

VPP

To Array

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