AD976/AD976A

–6–

REV. C

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Description

Analog Input. Connect a 200

Ω resistor between V

input range is

±10 V.

2

AGND1

Analog Ground. Used as the ground reference point for the REF pin.

3

REF

Reference Input/Output. The internal +2.5 V reference is available at this pin. Alternatively, an

external reference can be used to override the internal reference. In either case, connect a 2.2

µF

tantalum capacitor between REF and AGND1.

4

CAP

Reference Buffer Output. Connect a 2.2

µF tantalum capacitor between CAP and AGND2.

5

AGND2

Analog Ground.

6

D15 (MSB)

Data Bit 15. Most significant bit of conversion result. High impedance state when CS is HIGH or

when R/C is LOW.

7–13

D14–D8

Data Bits 14–8. High impedance state when CS is HIGH or when R/C is LOW.

14

DGND

Digital Ground.

15–21

D7–D1

Data Bits 7–1. High impedance state when CS is HIGH or when R/C is LOW.

22

D0 (LSB)

Data Bit 0. Least significant bit of conversion result. High impedance state when CS is HIGH or

when R/C is LOW.

23

BYTE

Byte Select. With BYTE LOW, data will be output as indicated above; Pin 6 (D15) is the MSB,

Pin 22 (D0) is the LSB. With BYTE HIGH, the top and bottom 8 bits of data will be switched;

D15–D8 are output on Pins 15–22 and D7–D0 are output on Pins 6–13.

24

R/C

Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the

hold state and starts a conversion; a rising edge enables the output data bits.

25

CS

Chip Select Input. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a

conversion. With R/C HIGH, a falling edge on CS will enable the output data bits. When CS is

HIGH, the output data bits will be in the Hi-impedance state.

26

BUSY

Busy Output. Goes LOW when a conversion is started and remains LOW until the conversion is

completed and the data is latched into the output register. With CS tied LOW and R/C HIGH,

output data will be valid when BUSY rises. The rising edge of BUSY can be used to latch the out-

put data.

27

Analog Power Supply. Nominally +5 V.

28

Digital Power Supply. Nominally +5 V.

DEFINITION OF SPECIFICATIONS

INTEGRAL NONLINEARITY ERROR (INL)

Linearity error refers to the deviation of each individual code

from a line drawn from “negative full scale” to “positive full

scale.” The point used as negative full scale occurs 1/2 LSB

before the first code transition. Positive full scale is defined as a

level 1 1/2 LSB beyond the last code transition. The deviation is

measured from the middle of each particular code to the true

straight line.

DIFFERENTIAL NONLINEARITY ERROR (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential

nonlinearity is the maximum deviation from this ideal value. It

is often specified in terms of resolution for which no missing

codes are guaranteed.

FULL-SCALE ERROR

The last + transition (from 011. . .10 to 011. . .11) should

occur for an analog voltage 1 1/2 LSB below the nominal full

scale (9.9995422 V for a

±10 V range). The full-scale error is

the deviation of the actual level of the last transition from the

ideal level.

BIPOLAR ZERO ERROR

Bipolar zero error is the difference between the ideal midscale

input voltage (0 V) and the actual voltage producing the midscale

output code.

INPUT BANDWIDTH

The input bandwidth is that frequency at which the amplitude

of the reconstructed fundamental is reduced by 3 dB for a full-

scale input.

FULL-POWER BANDWIDTH

Full-power bandwidth is defined as the full-scale input fre-

quency at which signal to (Noise + Distortion) degrades to

60 dB, as 10 bits of accuracy.

APERTURE DELAY

Aperture delay is a measure of the Sample-and-Hold Amplifier

(SHA) performance and is measured from the rising edge of the

clock input to when the input signal is held for a conversion.