AM29BDS323D datasheet(21/44 Pages) AMD

21 / 44 page

Am29BDS323D

P R E L I M INARY

WRITE OPERATION STATUS

The device provides several bits to determine the status of

a program or erase operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 6 and the following subsections describe the

function of these bits. DQ7 and DQ6 each offer a method

for determining whether a program or erase operation is

complete or in progress.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Program or Erase algo-

rithm is in progress or completed, or whether a bank is

in Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

g r am mi ng d u r i ng Er a s e Su sp en d. Whe n t h e

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then that bank returns to the read

mode.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

The system must provide an address within any of the

sectors selected for erasure to read valid status infor-

mation on DQ7. Note that the host system must wait

200 µs after the last sector erase command to obtain

status information if the first status read is in a different

bank than the last sector selected for erasure. For

example, if sector 0, which is in bank B, was the last

sector selected for erasure, and the host system

requests its first status read from sector 71, which is in

bank A, then the device requires 200 µs before status

information will be available.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs, then

the bank returns to the read mode. If not all selected

sectors are protected, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the

selected sectors that are protected. However, if the

system reads DQ7 at an address within a protected

sector, the status may not be valid.

Just prior to the completion of an Embedded Program

or Erase operation, DQ7 may change asynchronously

with DQ0–DQ6 while Output Enable (OE#) is asserted

low. That is, the device may change from providing

status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may read

the status or valid data. Even if the device has com-

pleted the program or erase operation and DQ7 has

valid data, the data outputs on DQ0–DQ6 may be still

invalid. Valid data on DQ0–DQ7 will appear on succes-

sive read cycles.

Table 6 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm. Figure 15

in the AC Characteristics section shows the Data#

Polling timing diagram.

Figure 3.

Data# Polling Algorithm

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is any sector address

within the sector being erased. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

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