ADM690–ADM695

REV. A

–12–

ADM690

ADM692

ADM694

R

2

R

1

PFO

+5V

V

CC

CMOS RAM

POWER

I/O LINE

µP NMI

µP RESET

µP SYSTEM

µP POWER

V

OUT

RESET

WDI

GND

PFI

V

BATT

BATTERY

+

0.1

µF

Figure 23a. ADM690/ADM692/ADM694 Typical Application

Circuit A

Figure 23b shows a similar application but in this case the PFI

input monitors the unregulated input to the 7805 voltage regu-

lator. This gives an earlier warning of an impending power fail-

ure. It is useful with processors operating at low speeds or

where there are a significant number of housekeeping tasks to be

completed before the power is lost.

ADM690

ADM692

ADM694

R

2

R

1

PFO

7805

INPUT

POWER

V > 8V

+5V

V

CC

CMOS RAM

POWER

I/O LINE

µP NMI

µP RESET

µP SYSTEM

µP POWER

V

OUT

RESET

WDI

GND

PFI

V

BATT

0.1

µF

BATTERY

0.1

µF

Figure 23b. ADM690/ADM692/ADM694 Typical Application

Circuit B

ADM691, ADM693, ADM695

A typical connection for the ADM691/ADM693/ADM695 is

output goes low, providing up to 25 mA of base drive for the

external transistor. A 0.1

µF capacitor is connected to V

Ω MOSFET connects the

µA

Note that the resistor will discharge the battery slightly. With a

Ω. With a 3 V

battery this will draw around 700 nA. This will be negligible in

most cases.

ADM69x

V

BATT

BATTERY

R

Figure 22b. Preventing Spurious RESETS During Battery

Replacement

TYPICAL APPLICATIONS

ADM690, ADM692 AND ADM694

Figure 23 shows the ADM690/ADM692/ADM694 in a typical

thereby maintaining power for the CMOS RAM. A RESET

ADM690/ADM694 or 4.4 V for the ADM692. RESET will

to 5 V.

The watchdog timer input (WDI) monitors an I/O line from the

µP system. This line must be toggled once every 1.6 seconds to

verify correct software execution. Failure to toggle the line indi-

cates that the

µP system is not correctly executing its program

and may be tied up in an endless loop. If this happens, a reset

pulse is generated to initialize the processor.

If the watchdog timer is not needed, the WDI input should be

left floating.

The Power Fail Input, PFI, monitors the input power supply via

a resistive divider network. The voltage on the PFI input is com-

pared with a precision 1.3 V internal reference. If the input volt-

age drops below 1.3 V, a power fail output (PFO) signal is

generated. This warns of an impending power failure and may

be used to interrupt the processor so that the system may be

shut down in an orderly fashion. The resistors in the sensing

network are ratioed to give the desired power fail threshold