AM29F400AB datasheet(15/35 Pages) AMD

15 / 35 page

Am29F400AT/Am29F400AB

PRELIMINARY

DQ7

Data Polling

The Am29F400A device features Data Polling as a

method to indicate to the host that the embedded algo-

rithms are in prog ress or completed. Dur ing

the Embedded Program Algorithm an attempt to read

the device will produce the complement of the data last

written to DQ7. Upon completion of the Embedded Pro-

gram Algorithm, an attempt to read the device will pro-

duce the true data last written to DQ7. During the

Embedded Erase Algorithm, an attempt to read

the device will produce a “0” at the DQ7 output.

Upon completion of the Embedded Erase Algorithm an

attempt to read the device will produce a “1” at the DQ7

output. The ﬂowchart for Data Polling (DQ7) is shown

in Figure 2.

For chip erase, the Data Polling is valid after the rising

edge of the sixth WE pulse in the six write pulse se-

quence. For sector erase, the Data Polling is valid after

the last rising edge of the sector erase WE pulse. Data

Polling must be performed at sector addresses within

any of the sectors being erased and not a protected

sector. Otherwise, the status may not be valid.

Just prior to the completion of Embedded Algorithm

operations DQ7 may change asynchronously while

the output enable (OE) is asserted low. This means

that the device is driving status information on DQ7 at

one instant of time and then that byte’s valid data at

the next instant of time. Depending on when the sys-

tem samples the DQ7 output, it may read the status or

valid data. Even if the device has completed the Em-

bedded Algorithm operations and DQ7 has a valid

data, the data outputs on DQ0–DQ6 may be still in-

valid. The valid data on DQ0–DQ7 will be read on the

successive read attempts.

The Data Polling feature is only active during the Em-

bedded Programming Algorithm, Embedded Erase Al-

gorithm, or sector erase time-out (see Table 7).

See Figure 10 for the Data Polling timing speciﬁcations

and diagrams.

DQ6

Toggle Bit

The Am29F400A also features the “Toggle Bit” as a

method to indicate to the host system that the embed-

ded algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cy-

cle, successive attempts to read (OE toggling) data

from the device at any address will result in DQ6 tog-

gling between one and zero. Once the Embedded Pro-

gram or Erase Algorithm cycle is completed, DQ6 will

stop toggling and valid data will be read on

the next

successive attempt. During programming, the Toggle

Bit is valid after the rising edge of the fourth WE pulse

in the four write pulse sequence. For chip erase, the

Toggle Bit is valid after the rising edge of the sixth WE

pulse in the six write pulse sequence. For Sector erase,

the Toggle Bit is valid after the last rising edge of the

sector erase WE pulse. The Toggle Bit is active during

the sector time-out.

Either CE or OE toggling will cause DQ6 to toggle. In

addition, an Erase Suspend/Resume command will

cause DQ6 to toggle. See Figure 11 for the Toggle Bit

timing speciﬁcations and diagrams.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has ex-

ceeded the speciﬁed limits (internal pulse count).

Under these conditions DQ5 will produce a “1”. This is

a failure condition which indicates that the program or

erase cycle was not successfully completed. Data Poll-

ing is the only operating function of the device under

this condition. The CE circuit will partially power down

the device under these conditions (to approximately 2

mA). The OE and WE pins will control the output dis-

able functions as described in Table 1.

The DQ5 failure condition will also appear if a user tries

to program a 1 to a location that is previously pro-

grammed to 0. In this case the device locks out and

never completes the Embedded Program Algorithm.

Hence, the system never reads a valid data on DQ7 bit

and DQ6 never stops toggling. Once the device has ex-

ceeded timing limits, the DQ5 bit will indicate a “1.”

Please note that this is not a device failure condition

since the device was incorrectly used. If this occurs,

reset the device.

DQ3

Sector Erase Timer

After the completion of the initial sector erase com-

mand sequence the sector erase time-out will begin.

DQ3 will remain low until the time-out is complete. Data

Polling and Toggle Bit are valid after the initial sector

erase command sequence.

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, DQ3 may be

used to determine if the sector erase timer window is

still open. If DQ3 is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent

commands (other than Erase Suspend) to the device

will be ignored until the erase operation is completed as

indicated by Data Polling or Toggle Bit. If DQ3 is low

(“0”), the device will accept additional sector erase

commands. To insure the command has been ac-

cepted, the system software should check the status of

DQ3 prior to and following each subsequent sector

erase command. If DQ3 were high on the second sta-

tus check, the command may not have been accepted.

Refer to Table 8: Write Operation Status.

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