AM7968 datasheet(21/127 Pages) AMD

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AMD

Am7968/Am7969

Am7969 Receiver Functional Block

Description

(Refer to page 1)

Crystal Oscillator/Clock Generator

The data recovery PLL in the Am7969 must be supplied

with a reference frequency at the expected byte rate of

the data to be recovered. The source of this frequency

can either be the built-in Crystal Oscillator, or an exter-

nal clock signal applied through the

X1 pin. The refer-

ence frequency source is then multiplied by ten (8-bit

mode), eleven (9-bit mode) or twelve (10-bit mode) us-

ing an internal PLL.

Media Interface

SERIN+, SERIN– inputs are to be driven by differential

ECL voltages, referenced to +5 V. Serial data at these

inputs will serve as the reference for PLL tracking.

PLL Clock Generator

A PLL Clock recovery loop follows the incoming data

and allows the encoded clock and data stream to be de-

coded into a separated clock and data pattern. It uses

the crystal oscillator and clock generator to predict the

expected frequency of data and will track jittered data

with a characteristically small offset frequency.

Shifter

The Shifter is serially loaded from the Media Interface,

using the bit clock generated by PLL.

Byte Sync Logic

The incoming data stream is a continuous stream of

data bits, without any significant signal which denotes

byte boundaries. This logic will continuously monitor the

data stream, and upon discovering the reserved code

used for Am7969 Receiver Sync, will initialize a

synchronous counter which counts bits, and indicates

byte boundaries.

The logic signal that times data transfers from the Shif-

ter to the Decoder Latch is buffered and sent to the

CLK

output.

CLK output from the Receiver is not suitable as a

frequency source for another TAXI Transmitter or Re-

ceiver. It is intended to be used by the host system as a

clock synchronous with the received data. This output is

synchronous with the byte boundary and is synchronous

with the Receiver’s internal byte clock.

Byte Sync Logic is responsible for generating the inter-

nal strobe signals for Parallel Output Latches. It also

generates the

IGM (I-Got-Mine) signal in Test mode

when the first byte after a Sync symbol is transferred.

Parallel outputs are made on a byte boundary, after

CNB falls, or when Sync is detected.

The I-Got-Mine (

IGM) signal will fall when the first half of

a Sync is detected in the Shifter or when

CNB goes

LOW. It will remain LOW until the first half of a non-Sync

byte is detected in the Shifter, whereupon it will rise (as-

suming that the

CNB input is HIGH). A continuous

stream of normal data or command bytes will cause

IGM

to go HIGH and remain HIGH. A continuous stream of

Sync’s will cause

IGM to stay LOW. IGM will go HIGH

during the byte before data appears at the output. This

feature could be used to generate an early warning of in-

coming data.

Decoder Latch

Data is loaded from the Shifter to this latch at each

symbol/byte boundary. It serves as the input to the

Data Decoder.

Data Decoder

Decodes ten, eleven, or twelve data inputs into twelve

outputs. In 8-bit mode, data is decoded into either an

8-bit Data pattern or a 4-bit Command pattern. In 9-bit

mode, data is decoded into either a 9-bit Data pattern or

a 3-bit Command pattern. In 10-bit mode, data is de-

coded into either a 10-bit Data pattern or a 2-bit Com-

mand pattern.

The decoder separates Data symbols from Command

symbols, and causes the appropriate strobe output to

be asserted.

Parallel Output Latch

Output Latch will be clocked by the byte clock, and will

reflect the most recent data on the link. Any Data pattern

will be latched to the Data outputs and will not affect the

status of the Command outputs. Likewise, any Com-

mand pattern will be latched to the Command outputs

without affecting the state of the Data outputs.

Any data transfer, either Data or Command will be syn-

chronous with an appropriate output strobe. However,

there will be

CSTRBs when there is no active data on the

link, since Sync is a valid Command code.

Any pattern which does not decode to a valid Command

or Data pattern is flagged as a violation. The output of

the decoder during these violations is indeterminate and

will result in either a

CSTRB or DSTRB output when the

indeterminate pattern is transferred to the output latch.

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