AMD

17

Am7992B

SWITCHING WAVEFORMS

(Note A) (Note E)

Bit Cell 1

1

Bit Cell 2

0

Bit Cell 3

1

Bit Cell 4

0

Bit Cell 5

1

BCC

1

BCB

BCC

0

BCB

BCC

1

BCB BCC

0

BCB

BCC

1

BCB

10

15

(Note D)

(Note B)

(Note C)

(Note F)

Receive

±

(Measured

Differentially)

INTCARR

RENA

INTRCLK

RCK Enable

RCLK

RX

INTPLLCLK

03378I-12

Notes:

A. Minimum Width > 45 ns.

B. RCLK = INTRCLK when

TEST LOW.

C. RX undefined until bit time 5 (1st decoded bit).

D. Oscillator Interrupt may occur at 2nd INTRCLK after Bit 2 Clock Transition.

E. Timing Diagram does not include Internal Propagation Delays.

F. First valid data at RX (Bit 5).

Receive Timing – Start of Reception Clock Acquisition