AM28F010-150ECB datasheet(14/35 Pages) AMD

14 / 35 page

Am28F010

Figure 2.

AC Waveforms For Erase Operations

Analysis of Erase Timing Waveform

Note: This analysis does not include the requirement

to program the entire array to 00h data prior to erasure.

Refer to the Flashrite Programming algorithm.

Erase Setup/Erase

This analysis illustrates the use of two-cycle erase

commands (section A and B). The first erase com-

mand (20h) is a Setup command and does not affect

the array data (section A). The second erase com-

mand (20h) initiates the erase operation (section B)

on the rising edge of this WE# pulse. All bytes of the

memory array are erased in parallel. No address infor-

mation is required.

The erase pulse occurs in section C.

Time-Out

A software timing routine (10 ms duration) must be ini-

tiated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibil-

ity of overerasure by limiting each time-out period of

10 ms.

Erase-Verify

Upon completion of the erase software timing routine,

the microprocessor must write the Erase-verify com-

mand (A0h). This command terminates the erase oper-

ation on the rising edge of the WE# pulse (section D).

The Erase-verify command also stages the device for

data verification (section F).

After each erase operation each byte must be verified.

The byte address to be verified must be supplied with

Addresses

Data

VPP

VCC

11559G-7

20h

Section

A0h

Data

Out

Bus Cycle

Write

Time-out

Write

Time-out

Read

Standby

Command

20h

N/A

A0h

N/A

Compare

Data

N/A

Function

Erase

Setup

Erase

(10 ms)

Erase-

Verify

Transition

(6 µs)

Erase

Verification

Proceed per

Erase

Algorithm

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