AM79C985 datasheet(47/48 Pages) AMD

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Am79C985

A-1

Appendix A

Security

EAVESDROP PROTECTION

The eIMR+/HIMIB devices are capable of providing

network eavesdrop protection. This feature is protected

by a software key. An application note containing the

necessary software key and implementation details is

available from AMD. A brief description of eavesdrop

protection is given below. For more information, contact

your local AMD sales representative.

FEATURES SUMMARY

Eavesdrop protection is based on the concept that con-

ﬁdential data should only be received by speciﬁed se-

cure stations. The eIMR+/HIMIB devices are capable of

repeating packets only to ports considered secure for a

packet’s destination address. On all other ports, trans-

mission can be disrupted by transmitting a pattern of

alternating 1s and 0s.

The eIMR+/HIMIB can disrupt packet transmission, as

described above, on ports not having a valid address.

Valid addresses are determined by comparing a

packet’s destination address with the two address reg-

isters associated with each repeater port: Last Source

Address Register and Preferred Source Address Reg-

ister. Eavesdrop protection can be masked on a port-

by-port basis. Disruption of multicast packets can also

be masked on a port-by-port basis. If the destination

address is a broadcast address, the packet is transmit-

ted unmodiﬁed on all ports.

In many instances, a station targeted with a speciﬁc

destination address will not reside within the same re-

peater as the originating station. To ensure that packets

arrive at the intended destination, eIMR+/HIMIB ports

can be programmed to pass packets with an invalid des-

tination address undisturbed if no other port on the re-

peater has a valid address that matches the destination

address. The eIMR+/HIMIB devices can determine if

there is a match on the repeater by monitoring its ports

and by monitoring signals on the eIMR+/HIMIB expan-

sion bus.

Figure A1.

STR Input Signal from Am79C987 HIMIB Device

AUI

TP0

TP1

TP2

TP3

TP4

TP5

TP6

TP7

CLK

TCLK

STR

Note: TCLK illustrates internal eIMR+ chip clock phase relationship.

20651B-34

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