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CD00257532 数据表(PDF) 6 Page - STMicroelectronics |
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CD00257532 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 19 page ![]() Block diagram and pin description L4949ED-E, L4949EP-E 6/19 Doc ID 16823 Rev 1 Table 2. Pin definitions and functions Pin N° Symbol Function SO-8 SO-20 119 VS Input supply voltage. Block to GND via an external capacitor (see Figure 3). 220 SI Sense input pin to supervise input voltage. Connect via an external voltage divider connected to VS and to GND. 31 VZ Preregulator output voltage. For details, see Section 3.4: Preregulator. 42 CT Reset pulse delay adjustment. Connecting this pin via a capacitor to GND 5 4, 5, 6, 7, 14, 15, 16, 17 GND Ground reference 610 RES Reset output. It is pulled down when the output voltage goes below VRT. 711 SO Sense output. This open collector pin must be connected to VOUT via an external resistor. It is pulled down whenever the SI voltage becomes lower than an internal voltage. 812 VOUT Output voltage. Block to GND via an external capacitor (see Figure 3) - 3, 8, 9, 13, 18 NC Not connected pins |
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