AM29F010B datasheet(15/31 Pages) AMD

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Am29F010

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE# pulse in the com-

mand sequence (prior to the program or erase opera-

tion), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read cycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles for approximately 100

µs, then returns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2

µs after the program

command sequence is written, then returns to reading

array data.

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 4 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, a

system would note and store the value of the toggle

bit after the first read. After the second read, the sys-

tem would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

device did not complete the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 4).

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle?

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

16736G-10

Figure 4.

Toggle Bit Algorithm

(Notes

1, 2)

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