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A29DL323 数据表(PDF) 5 Page - AMIC Technology

部件名 A29DL323
功能描述  32M-Bit CMOS Low Voltage Dual Operation Flash Memory 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit (Word Mode)
PDF  46 Pages
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制造商  AMICC [AMIC Technology]
网页  http://www.amictechnology.com
标志 AMICC - AMIC Technology

A29DL323 数据表(HTML) 5 Page - AMIC Technology

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A29DL323 Series
PRELIMINARY
(May, 2002, Version 0.0)
5
AMIC Technology, Inc.
Absolute Maximum Ratings*
Storage Temperature (Tstg) . . . . . . . . . . -55
°C to + 125°C
Operating Ambient Temperature (TA) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
°C to + 85°C
Input / Output Voltage with Respect to GND
WP (ACC),
RESET . . . . . . . . . . . . -0.5V
Note1 to 13.0V
All Pins except
WP (ACC), RESET . . . . . . . . . . . . . . .
. . . . . . . . . . . . . -0.5V
Note1 to VCC + 0.4 (4.0V max.) Note2
Supply Voltage with Respect to GND (VCC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V
Notes:
1.
-2.0V (Min.) (Pulse width
≤ 20ns)
2.
VCC + 0.5V (Max.) (Pulse width
≤ 20ns)
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
Operating Ambient Temperature (TA) . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40
°C to +85°C
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . +2.7V to +3.6V
Bus Operations
The following table shows the operation modes of the dual
operation flash memory. Before turning on power, input
GND
± 0.2 V to the RESET until VCC ≥ VCC (min.).
Table 1. A29DL323 Bus Operations
Operation
CE
OE
WE
I/O15,
A-1
A6
A1
A0
I/O0 to
I/O7
I/O8 to
I/O15
RESET
WP
(ACC)
BYTE mode
L
L
H
A-1
Address input
Data output
Hi-Z
H
X
Read (Note)
WORD mode
L
L
H
X
Address input
Data output
H
X
Write
BYTE mode
L
H
L
A-1
Address input
Data input
Hi-Z
H
Note3
WORD mode
L
H
L
X
Address input
Data input
H
Note3
Standby
H
X
X
X
X
X
X
Hi-Z
Hi-Z
H
X
Hardware reset / Standby
X
X
X
X
X
X
X
Hi-Z
Hi-Z
L
X
Output Disable
L
H
H
X
X
X
X
Hi-Z
Hi-Z
H
X
Temporary Sector Group Unprotect
X
X
X
X
X
X
X
Hi-Z or
Data input / output
VID
Note3
BYTE mode
L
L
H
A-1
Address input
Data output
Hi-Z
H
X
Automatic Sleep
Mode
WORD mode
L
L
H
X
Address input
Data output
H
X
Boot Block Sector Protect
X
X
X
X
X
X
X
Hi-Z or
Data input / output
X
L
BYTE mode
L
H
L
A-1
Address input
Data input
Hi-Z
H
VACC
Accelerated Mode
WORD mode
L
H
L
X
Address input
Data input
H
VACC
Note: When OE = VIL, VIL can be applied to WE . When OE = VIH, a write operation is started.
Remarks: 1. H : VIH, L : VIL, : VIH or VIL, VID : 11.5 V to 12.5 V, VACC : 8.5 V to 9.5 V
2. If an address is held longer than the minimum read cycle time (tRC), the automatic sleep mode is set.
3. If
WP (ACC)=VIL, sector 0,1,140, and 141 remain protected. If WP (ACC)=VIH, protection on sectors 0,1,140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If
WP (ACC)=VHH, all sectors will be unprotected.



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