7290-072011-2

VREF Input

External voltage reference for chopper circuit which determines the

maximum motor winding current by regulating the PWM duty cycle. The

These three pins can be configured in one of three ways to obtain the

primary clock. A crystal connected between RX and CLK pins or a

resistor-capacitor pair connected among all three pins (see Figure 4) can

make use of the internal oscillator. Alternatively, the CLK pin can be

driven from an external clock source.

DS0/DS1 Inputs

The phase drive is blanked out between steps by switching outputs INH1

and INH2 low in order to reduce audible noise and power consumption.

The duration of the blanking is selected by DS0 and DS1 according to

Table 1.

DS1 DS0

0

0

1.25

μs

0

1

2.50

μs

1

0

3.75

μs

1

1

5.00

μs

PHA / PHB / PHC / PHD Outputs

The state of these phase outputs are determined by the look-up

table and are used to control either the left or right half of each

of the H-Bridge drivers. A low on a phase output enables the

bottom driver while a high on the output enables the top driver.

HOME Output

Indicates Step0 state per Table 2 with a logic low.

INH1 / INH2 Outputs

These outputs are used to provide PWM control to each of the

two H-Bridge drivers.

Table 1

The information included herein is believed to be accurate and reliable.

However, LSI Computer Systems, Inc. assumes no responsibilities for

inaccuracies, or for any infringements of patent rights of others which may

result from its use.

FIGURE 2. LS7290 BLOCK DIAGRAM