PHA/PHB/PHC/PHD

Phase drive output signals for power stages. In a Bipolar motor

PHA and PHB are used for one H-bridge while PHC and PHD

are used for the other.

INH1/INH2 Outputs

These outputs are active low inhibit controls for motor drive

outputs. INH1 controls driver stage using PHA and PHB sig-

nals while INH2 control driver stage using PHC and PHD sig-

nals. When the Control input is low, these outputs are chopped

using the internal oscillator for current regulating.

CONTROL Input

When high, the phase outputs, PHA, PHB, PHC and PHD are

chopped. When low, INH1 and INH2 are chopped. Normally,

inhibit outputs are chopped. Phase chopping might be used

with a Bipolar motor that does not store much energy to pre-

vent fast current decay and a low useful torque.

ENABLE Input

When Enable input is low, INH1, INH2, PHA, PHB, PHC and

PHD are brought low.

HOME Output

An open drain output that indicates when the

LS8297 is in its

initial state with PHA, PHB, PHC, PHD = logic states 0101 re-

spectively. Refer to Figure 4. In the active state the open drain

device is off.

STEP Input

An active low pulse on this input causes the motor to ad-

vance one step. The step occurs on the rising edge of the

step signal.

FRD/REV Input

A logic 1 on this input causes the motor to advance through

the stepping sequence of Fig. 4. A logic 0 on this input cause

the motor to reverse the sequence.

RESET Input

An active low on this input cause the motor to be restored to

the home position (0101).

HALF/FULL Input

When high, half-step operation is selected. When low, full-

step operation is selected. One-phase on full step is selected

by selecting full when stepping sequence is at an even state.

Two-phase on full step operation is selected when stepping

sequence is at an odd state. Refer to Figure 4.

SENSE1/ SENSE2 Inputs

Inputs for load current sense voltages from power stages us-

ing PHA and PHB drive signals or PHC and PHD drive sig-

nals, respectively.

Reference voltage for chopper circuit which determines the

peak load current.

8297-091608-2

FIGURE 2. LS8297/LS8297CT BLOCK DIAGRAM

OUTPUT LOGIC

TRANSLATOR

+

-

14

13

16

SENSE1

SENSE2

OSC

3

17

20

19

12

4

9

5

6

7

8

PHA INH1 PHB PHC

PHD

INH2

HALF/FULL

RESET

FWD/REV

STEP

HOME

18

OSC

S

Q

R

FF1

R

S

Q

FF2

1

10

+

-

SYNC

CONTROL

11

ENABLE

MUX

x0.707

15

2

+V