PIC16LF1906-EPSQTP datasheet(61/288 Pages) MICROCHIP

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Preliminary

DS41569A-page 61

PIC16LF1904/6/7

6.2.2.2

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 6-1). Select 31 kHz, via

software, using the IRCF<3:0> bits of the OSCCON

Clock Switch Timing”

for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT) and Watchdog Timer (WDT).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register = 000) as the

system clock source (SCS bits of the OSCCON

• Configure the IRCF<3:0> bits of the OSCCON

•FOSC<1:0> = 01, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘1x’

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

6.2.2.3

Internal Oscillator Frequency

Selection

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 6-1). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

the following frequencies can be selected via software:

•16 MHz

•8 MHz

•4 MHz

•2 MHz

•1 MHz

• 500 kHz (default after Reset)

• 250 kHz

• 125 kHz

• 62.5 kHz

• 31.25 kHz

• 31 kHz (LFINTOSC)

The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These dupli-

cate choices can offer system design trade-offs. Lower

power consumption can be obtained when changing

oscillator sources for a given frequency. Faster transi-

tion times can be obtained between frequency changes

that use the same oscillator source.

6.2.2.4

Internal Oscillator Clock Switch

Timing

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 6-4). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The OSCSTAT register will

reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency

selection is as follows:

IRCF<3:0> bits of the OSCCON register are

modified.

If the new clock is shut down, a clock start-up

delay is started.

Clock switch circuitry waits for a falling edge of

the current clock.

The current clock is held low and the clock

switch circuitry waits for a rising edge in the new

clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 6-4 for more details.

If the internal oscillator speed is switched between two

clocks of the same source, there is no start-up delay

before the new frequency is selected. Clock switching

time delays are shown in Table 6-1.

Start-up delay specifications are located in the

oscillator

tables

Section 22.0

“Electrical

Specifications”

Note:

Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to ‘0111’

and the frequency selection is set to

500 kHz. The user can modify the IRCF

bits to select a different frequency.

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