AP160

Version 0.0

13

AMIC Technology, Inc.

DATA MEMORY

The AP160 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special

Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically

separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used

in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use

direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location

0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing

instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are avail-able as stack

space.

POWER MANAGEMENT

IDLE MODE

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software.

The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode

can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware

reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal

reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is

not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the

instruction following the one that invokes idle mode should not write to a port pin or to external memory.

POWER DOWN MODE

In the power down mode, the oscillator is stopped, and the instruction that invokes power down is the last instruction

executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated.

The way to exit from power down mode is either hardware reset or external interrupt. Reset redefines the SFRs but does not

change the on-chip RAM. The reset should not be activated before V CC is restored to its normal operating level and must

be held active long enough to allow the oscillator to restart and stabilize.

Status of External Pins During Idle and Power Down Modes

Mode

Program Memory

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Idle

Internal

1

1

Data

Data

Data

Data

Idle

External

1

1

Float

Data

Address

Data

Power Down

Internal

0

0

Data

Data

Data

Data

Power Down

External

0

0

Float

Data

Data

Data

RESET

A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the

oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to

start up (normally a few milliseconds) plus two machine cycles.

REDUCED EMI

All port pins of the AP160 have slew rate controlled outputs. This is to limit noise generated by quickly switching output

signals. The slew rate is factory set to approximately 10 ns rise and fall times.

AUXR Address = 8EH

Bit

7

6

5

4

3

2

1

0

-

-

-

-

-

-

-

AO

NOTE: The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.