LP61L1008 Series

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

(June, 2002, Version 2.0)

1

AMIC Technology, Inc.

Features

General Description

n Access times: 12/15 ns (max.)

n Current: Operating: 180mA (max.)

Standby:

5mA (max.)

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL compatible

n Center Power/Ground Pin Configuration

n Common I/O using three-state output

n Output enable and two chip enable inputs for easy

application

n Data retention voltage: 2.0V (min.)

n Available in 32-pin SOJ 300 mil and 32-pin sTSOP

packages

The LP61L1008 is a high speed 1,048,576-bit static

random access memory organized as 131,072

words by 8 bits and operates on a single 3.3V power

supply.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

The chip enable input is provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage

as low as 2.0V.

Product Family

Power Dissipation

Product

Family

Operating

Temperature

VCC

Range

Speed

Data Retention

Standby

Operating

Package

Type

LP61L1008

0

°C~70°C

3.0V~3.6V

12/15 ns

10

µA

20

µA

66mA

32L SOJ

32L sTSOP

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

Pin Configuration

n

n SOJ

n

n sTSOP

A0

A1

A2

A3

CE

VCC

GND

WE

A4

A5

A6

A8

A7

A9

A10

A11

A12

VCC

OE

A13

A14

A15

A16

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A15

VCC

A16

A14

LP61L1008X

1

9

32

24

A0

A1

2

3

4

5

6

7

8

10

11

12

13

14

15

16

A2

A3

VCC

VSS

A4

A5

A6

A7

31

30

29

28

27

26

25

23

22

21

20

19

18

17

A13

OE

VSS

A11

A10

A9

A8

CE

A12

WE