STM32F215RG datasheet(32/175 Pages) STMICROELECTRONICS

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Functional overview

STM32F21xxx

32/175

DocID17050 Rev 9

The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the

SD Memory Card Specification Version 2.0.

The SDIO Card Specification Version 2.0 is also supported with two different databus

modes: 1-bit (default) and 4-bit.

The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack

of MMC4.1 or previous.

In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital

protocol Rev1.1.

3.26

Ethernet MAC interface with dedicated DMA and IEEE 1588

support

Peripheral available only on the STM32F217xx devices.

The STM32F217xx devices provide an IEEE-802.3-2002-compliant media access controller

(MAC) for ethernet LAN communications through an industry-standard medium-

independent interface (MII) or a reduced medium-independent interface (RMII). The

STM32F217xx requires an external physical interface device (PHY) to connect to the

physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F217xx MII

port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz

(MII) or 50 MHz (RMII) output from the STM32F217xx.

The STM32F217xx includes the following features:

•

Supports 10 and 100 Mbit/s rates

•

Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM

and the descriptors (see the STM32F20x and STM32F21x reference manual for

details)

•

Tagged MAC frame support (VLAN support)

•

Half-duplex (CSMA/CD) and full-duplex operation

•

MAC control sublayer (control frames) support

•

32-bit CRC generation and removal

•

Several address filtering modes for physical and multicast address (multicast and

group addresses)

•

32-bit status code for each transmitted or received frame

•

Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the

receive FIFO are both 2 Kbytes, that is 4 Kbytes in total

•

Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008

(PTP V2) with the time stamp comparator connected to the TIM2 input

•

Triggers interrupt when system time becomes greater than target time

3.27

Controller area network (CAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

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