STM32F415OG datasheet(118/186 Pages) STMICROELECTRONICS

118 / 186 page

Electrical characteristics

STM32F415xx, STM32F417xx

118/186

DocID022063 Rev 4

Figure 39. I2C bus AC waveforms and measurement circuit

1. Rs= series protection resistor.

2. Rp = external pull-up resistor.

3. VDD_I2C is the I2C bus power supply.

th(STA)

Start condition hold time

4.0

0.6

µs

tsu(STA)

Repeated Start condition

setup time

4.7

0.6

tsu(STO)

Stop condition setup time

4.0

0.6

μs

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

μs

Capacitive load for each bus

line

400

1. Guaranteed by design, not tested in production.

2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to

achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode

clock.

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

Table 53. I2C characteristics (continued)

Symbol

Parameter

Standard mode I2C(1)

Fast mode I2C(1)(2)

Unit

Min

Max

Min

Max

ai14979c

ST AR T

SD A

I²C bus

V DD_I2C

STM32Fxx

SDA

SCL

tf(SDA)

tr(SDA)

SCL

th(STA)

tw(SCLH)

tw(SCLL)

tsu(SDA)

tr(SCL)

tf(SCL)

th(SDA)

S T AR T REPEATED

ST AR T

tsu(STA)

tsu(STO)

STOP

tw(STO:STA)

V DD_I2C

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