STM32F207VC datasheet(161/163 Pages) STMICROELECTRONICS

161 / 163 page

STM32F205xx, STM32F207xx

Revision history

Doc ID 15818 Rev 7

161/163

22-Apr-2011

(continued)

Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and

tf(SCK) to tf(SCL) in Table 47: I2C characteristics and in Figure 38: I2C

bus AC waveforms and measurement circuit.

Added Table 52: USB OTG FS DC electrical characteristics and

updated Table 53: USB OTG FS electrical characteristics.

Updated VDD minimum value in Table 57: Ethernet DC electrical

characteristics.

Updated Table 61: ADC characteristics and RAIN equation.

Updated RAIN equation. Updated Table 63: DAC characteristics.

Updated tSTART in Table 64: TS characteristics.

Updated R typical value in Table 65: VBAT monitoring characteristics.

Updated Table 66: Embedded internal reference voltage.

Modified FSMC_NOE waveform in Figure 54: Asynchronous non-

multiplexed SRAM/PSRAM/NOR read waveforms. Shifted end of

FSMC_NEx/NADV/addresses/NWE/NOE/NWAIT of a half FSMC_CLK

period, changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-

AIV), td(CLKH-NOEH) to td(CLKL-NOEH), and td(CLKH-NWEH) to td(CLKL-

NWEH), and updated data latency from 1 to 0 in Figure 58:

Synchronous multiplexed NOR/PSRAM read timings, Figure 59:

Synchronous multiplexed PSRAM write timings, Figure 60:

Synchronous non-multiplexed NOR/PSRAM read timings, and

Figure 61: Synchronous non-multiplexed PSRAM write timings,

Changed td(CLKH-NExH) to td(CLKL-NExH), td(CLKH-AIV) to td(CLKL-AIV),

td(CLKH-NOEH) to td(CLKL-NOEH), td(CLKH-NWEH) to td(CLKL-NWEH), and

modified tw(CLK) minimum value in Table 71, Table 72, Table 73, and

Table 74.

Updated note 2 in Table 67, Table 68, Table 69, Table 70, Table 71,

Table 72, Table 73, and Table 74.

Modified th(NIOWR-D) in Figure 67: PC Card/CompactFlash controller

waveforms for I/O space write access.

Modified FSMC_NCEx signal in Figure 68: NAND controller

waveforms for read access, Figure 69: NAND controller waveforms for

write access, Figure 70: NAND controller waveforms for common

memory read access, and Figure 71: NAND controller waveforms for

common memory write access

Specified Full speed (FS) mode for Figure 88: USB OTG HS

peripheral-only connection in FS mode and Figure 89: USB OTG HS

host-only connection in FS mode.

Table 89.

Document revision history (continued)

Date

Revision

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