ThunderLAN

™ TNETE100

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

™

SPWS017B – APRIL 1995 – REVISED AUGUST 1996

12

POST OFFICE BOX 1443

– 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (see Note 2)

– 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range

– 0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation

1.6 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

°C to 95°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28.8

°C/W

. . . . . . . . . . . . . . . . . . . .

24.8

°C/W

. . . . . . . . . . . . . . . .

2.0

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 2: Voltage values are with respect to VSS, and all VSS pins should be routed so as to minimize inductance to system ground.

The recommended operating conditions and the electrical characteristics tables are divided into groups,

depending on pin function:

The PCI signal pins may be operated in one of two modes shown in the PCI tables.

recommended operating conditions (PCI interface pins only) (see Note 3)

3-V SIGNALING

OPERATION

5-V SIGNALING

OPERATION

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

VDD

Supply voltage (PCI)

3

3.3

3.6

4.75

5

5.25

V

VIH

High-level input voltage

0.5

 VDD‡

VDD + 0.5‡

2.0

VDD + 0.5

V

VIL

Low-level input voltage, TTL-level signal (see Note 4)

– 0.5‡

0.5‡

– 0.5

0.8

V

IOH

High-level output current

TTL outputs

– 0.5

–2

mA

IOL

Low-level output current (see Note 5)

TTL outputs

1.5

6

mA

‡ Assured by design SPICE IV Curve (See PCI specification revision 2.1 section 4.2 paragraph 2 for explanation.)

NOTES:

3. PCI interface pins include VDDI, PCLKRUN, PFRAME, PTRDY, PIRDY, PSTOP, PDEVSEL, PIDSEL, PPERR, PSERR, PREQ,

PGNT, PCLK, PPAR, PRST, PINTA, PAD[31 : 0], and PC/BE[3 : 0].

4. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels

only.

5. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst

case).