SPC5643AF0MMG2 datasheet(6/138 Pages) FREESCALE

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MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

1.4

Feature details

1.4.1

e200z4 core

MPC5644A devices have a high performance e200z448n3 core processor:

•

Dual issue, 32-bit Power Architecture embedded category CPU

•

Variable Length Encoding Enhancements

•

8 KB instruction cache: 2- or 4- way set associative instruction cache

•

Thirty-two 64-bit general purpose registers (GPRs)

•

Memory management unit (MMU) with 24-entry fully-associative translation look-aside buffer (TLB)

•

Harvard Architecture: Separate instruction bus and load/store bus

•

Vectored interrupt support

•

Non-maskable interrupt input

•

Critical Interrupt input

•

New ‘Wait for Interrupt’ instruction, to be used with new low power modes

•

Reservation instructions for implementing read-modify-write accesses

•

Signal processing extension (SPE) APU

•

Single Precision Floating point (scalar and vector)

•

Nexus Class 3+ debug

•

Process ID manipulation for the MMU using an external tool

1.4.2

Crossbar Switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between five master ports and four slave ports. The

crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access

a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher

priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher

priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave

port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following

features:

•

5 master ports

— CPU instruction bus

— CPU data bus

—eDMA

—FlexRay

— External Bus Interface

•

4 slave ports

—Flash

— Calibration and EBI bus

—SRAM

— Peripheral bridge

•

32-bit internal address, 64-bit internal data paths

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