3

OSCILLATOR

OSC

CLOCK

GENERATOR

CONTROL

LOGIC

TG1

TG2

TG3

TG4

SBT

IRP

OUTPUT

DRIVER

OUT1

OUT2

OUT3

POP NOISE

REDUCTION

ADDRESS

SEQUENCER

VOICE

EPROM

ADPCM

DECODER

BUZZER

BUFFER

D/A

GND

BLOCK DIAGRAM

PIN DESCRIPTION

OUT1

Programmable output 1

OUT2

Programmable output 2

OUT3

Programmable output 3

PWM audio signal output for buzzer and speaker

PWM audio signal output for buzzer and speaker

GND

Power ground

Current output from internal DAC for speaker playback

OSC

Oscillator resistor pin to control sampling frequency

Program power supply, no connect when voice playback

TG1

Trigger switch 1, internal pull low, active high

Trigger switch 2, internal pull low, active high

Positive power supply

TG3

Trigger switch 3, internal pull low, active high

TG4

Trigger switch 4, internal pull low, active high

SBT

Sequential trigger, internal pull low, active high

IRP

Interrupt to stop playback, internal pull low, active high

Note:

1. The following pins are used to program data into the memory:

pins 4, 5, 6, 8, 9, 12, 15 and 16.

PIN CONFIGURATIONS

300-mil PDIP

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

OUT1

GND

OUT2

OUT3

OSC

IRP

SBT

TG4

TG3

TG2

TG1

APLUS

API8208A

TG2