LPC2104FBD48SLASH00 datasheet(22/41 Pages) PHILIPS

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LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

22 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,

it is insured that the PLL output has a 50 % duty cycle.The PLL is turned off and bypassed

following a chip Reset and may be enabled by software. The program must conﬁgure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100

µs.

6.18.3 Reset and wake-up timer

Reset has two sources on the LPC2104/2105/2106: the RESET pin and Watchdog Reset.

The RESET pin is a Schmitt trigger input pin with an additional glitch ﬁlter. Assertion of

chip Reset by any source starts the wake-up timer (see wake-up timer description below),

causing the internal chip reset to remain asserted until the external Reset is de-asserted,

the oscillator is running, a ﬁxed number of clocks have passed, and the on-chip ﬂash

controller has completed its initialization.

When the internal Reset is removed, the processor begins executing at address 0, which

is the Reset vector. At that point, all of the processor and peripheral registers have been

initialized to predetermined values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This

is important at power on, all types of Reset, and whenever any of the aforementioned

functions are turned off for any reason. Since the oscillator and other functions are turned

off during Power-down mode, any wake-up of the processor from Power-down mode

makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is

safe to begin code execution. When power is applied to the chip, or some event caused

the chip to exit Power-down mode, some time is required for the oscillator to produce a

signal of sufﬁcient amplitude to drive the clock logic. The amount of time depends on

many factors, including the rate of VDD ramp (in the case of power on), the type of crystal

and its electrical characteristics (if a quartz crystal is used), as well as any other external

circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing

ambient conditions.

6.18.4 Code security (Code Read Protection - CRP)

This feature of the LPC2104/2105/2106/01 allows the user to enable different levels of

security in the system so that access to the on-chip ﬂash and use of the JTAG and ISP

can be restricted. When needed, CRP is invoked by programming a speciﬁc pattern into a

dedicated ﬂash location. IAP commands are not affected by the CRP.

There are three levels of the Code Read Protection:

1. CRP1 disables access to the chip via the JTAG and allows partial ﬂash update

(excluding ﬂash sector 0) using a limited set of the ISP commands. This mode is

useful when CRP is required and ﬂash ﬁeld updates are needed but all sectors can

not be erased.

2. CRP2 disables access to the chip via the JTAG and only allows full ﬂash erase and

update using a reduced set of the ISP commands.

LPC2104FBD48/00 数据表(PDF) 22 Page - NXP Semiconductors

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