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AD5331 数据表(PDF) 5 Page - Analog Devices |
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AD5331 数据表(HTML) 5 Page - Analog Devices |
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5 / 24 page  AD5346/AD5347/AD5348 Rev. 0 | Page 5 of 24 TIMING CHARACTERISTICS1, 2, 3 Table 3. VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted Parameter Limit at TMIN, TMAX Unit Condition/Comments Data Write Mode (Figure 3) t1 0 ns min CS to WR setup time t2 0 ns min CS to WR hold time t3 20 ns min WR pulse width t4 5 ns min Data, GAIN, BUF setup time t5 4.5 ns min Data, GAIN, BUF hold time t6 5 ns min Synchronous mode. WR falling to LDAC falling. t7 5 ns min Synchronous mode. LDAC falling to WR rising. t8 4.5 ns min Synchronous mode. WR rising to LDAC rising. t9 5 ns min Asynchronous mode. LDAC rising to WR rising. t10 4.5 ns min Asynchronous mode. WR rising to LDAC falling. t11 20 ns min LDAC pulse width t12 10 ns min CLR pulse width t13 20 ns min Time between WR cycles t14 20 ns min A0, A1, A2 setup time t15 0 ns min A0, A1, A2 hold time Data Readback Mode (Figure 4) t16 0 ns min A0, A1, A2 to CS setup time t17 0 ns min A0, A1, A2 to CS hold time t18 0 ns min CS to falling edge of RD t19 20 ns min RD pulse width; VDD = 3.6 V to 5.5 V 30 ns min RD pulse width; VDD = 2.5 V to 3.6 V t20 0 ns min CS to RD hold time t21 22 ns max Data access time after falling edge of RD; VDD = 3.6 V to 5.5 V 30 ns max Data access time after falling edge of RD VDD = 2.5 V to 3.6 V t22 4 ns min Bus relinquish time after rising edge of RD 30 ns max t23 22 ns max CS falling edge to data; VDD = 3.6 V to 5.5 V 30 ns max CS falling edge to data; VDD = 2.5 V to 3.6 V t24 30 ns min Time between RD cycles t25 30 ns min Time from RD to WR t26 30 ns min Time from WR to RD, VDD = 3.6 V to 5.5 V 50 ns min Time from WR to RD, VDD = 2.5 V to 3.6 V 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. CS WR DATA, GAIN, BUF LDAC1 LDAC2 CLR NOTES 1. SYNCHRONOUS LDAC UPDATE MODE 2. ASYNCHRONOUS LDAC UPDATE MODE A0–A2 t1 t2 t3 t4 t7 t9 t10 t11 t12 t5 t15 t8 t14 t6 t13 CS A0–A2 RD WR DATA t16 t18 t25 t20 t22 t21 t17 t26 t24 t19 t23 Figure 3. Parallel Interface Write Timing Diagram Figure 4. Parallel Interface Read Timing Diagram |
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